Low power processor

• US 20040158756A1
• Filed: 02/02/2004
• Published: 08/12/2004
• Est. Priority Date: 11/21/1996
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishibashi, Koichiro, Uchiyama, Kunio, Nishii, Osamu, Shimura, Takanori, Mizuno, Hiroyuki, Totsuka, Yonetaro, Sekine, Asako, Katsuki, Yoichi, Narita, Susumu
• Granted Patent: US 7,475,261 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Claims

1. A microprocessor comprising:

a main circuit including transistors;

a substrate bias switching circuit for switching voltages of substrate biases applied to a substrate of said main circuit; and

an operation mode control circuit for controlling, in response to execution of an instruction to proceed to a first mode in said main circuit, said substrate bias switching circuit in such a way that the substrate biases are switched over to voltages for the first mode, and for controlling, in response to execution of an instruction to proceed to a second mode in said main circuit, said substrate bias switching circuit in such a way that the substrate biases are switched over to voltages for the second mode, and also for starting, when switching the substrate biases from the voltages for the first mode over to the voltages for the second mode, the operation of said transistors of said main circuit after the bias voltages switched thereto have been stabilized.

2. A microprocessor according to claim 1, wherein the substrate in which said microprocessor is formed has a triple well structure in which a second semiconductor region of a second type is formed within a first semiconductor region of a first type, and a third semiconductor region of the first type is formed within said semiconductor region of the second type.

3. A microprocessor according to claim 2, wherein an n-channel transistor is formed on said second semiconductor region and also a p-channel transistor is formed on said third semiconductor region.

4. A microprocessor according to claim 2 or 3, wherein said substrate bias switching circuit controls a voltage applied to said second semiconductor region and a voltage applied to said third semiconductor region.

5. A microprocessor according to one of claims 1 to 4, wherein said main circuit is formed on a well region which is different from those of said substrate bias switching circuit and said operation mode control circuit.

6. A microprocessor according to one of claims 1 to 5, wherein said operation mode control circuit includes a timer for measuring a lapse of a time period required for stabilization of the biases.

7. A microprocessor according to one of claims 1 to 5, wherein said operation mode control circuit includes a sensor for detecting that the biases have been-stabilized to predetermined voltages, respectively.

8. A microprocessor according to one of claims 1 to 7, wherein said substrate bias switching circuit includes a substrate bias generating circuit for generating voltages for the substrate biases.

9. A microprocessor according to one of claims 1 to 8, wherein said first mode is a stand-by mode wherein the operation of said main circuit becomes stand-by, and also said second mode is a normal mode wherein said main circuit carries out a normal operation.

10. A microprocessor according to one of claims 1 to 9, wherein said first mode is a state in which the power consumption of said main circuit becomes smaller than that in said second mode.

11. A microprocessor according to one of claims 1 to 10, wherein said main circuit includes:

a CPU, a cache memory for inputting/outputting data to/from said CPU, an interruption control circuit for controlling an interruption input, and a clock control circuit for controlling a clock.

12. A microprocessor according to claim 11, wherein in said first mode, the clock for said main circuit is stopped.

13. A microprocessor according to one of claims 1 to 12, further comprising a battery as the power source of said main circuit, and a monitoring circuit for monitoring a voltage of said battery, wherein when the voltage of said battery is reduced to a level lower than a predetermined value, said second mode is switched over to said first mode on the basis of a control signal from said monitoring circuit.

14. A microprocessor according to claim 12, wherein after having stopped the clock for said main circuit, the operation mode enters into said first mode.

15. A microprocessor comprising:

a processor main circuit for executing program instruction strings;

a substrate bias control circuit for controlling substrate biases applied to a substrate on which said processor main circuit is formed; and

an operation mode control unit for controlling said substrate bias control circuit in such a way that said processor main circuit is controlled so as to obtain voltages for a stand-by mode, and for controlling, in response to an interruption for the stand-by release from the outside, said substrate bias control circuit in such a way that the voltages for the stand-by mode are switched over to voltages for a normal mode,

wherein said operation mode control unit releases the stand-by of said main circuit after the voltages for the normal mode have been stabilized.

16. A semiconductor integrated circuit device having a first circuit block including transistors and a second circuit block for exchanging signals between said first circuit block and said second circuit block, said device comprising:

a substrate bias generating circuit for applying substrate bias voltages to a semiconductor substrate on which the transistors of said first circuit block are formed; and

output fixing circuits for fixing, when said substrate bias generating circuit changes the substrate bias voltages, levels of at least part of the signals which are inputted from said second circuit block to said first circuit block.

17. A semiconductor integrated circuit device according to claim 16, wherein said first circuit block is different in operation voltages from said second circuit block.

18. A semiconductor integrated circuit device according to claim 16 or 17, further comprising an operation mode control unit for receiving, as an input, a substrate bias in-control signal from said substrate bias control circuit, wherein said output fixing circuits are controlled on the basis of a signal fixing signal from said operation mode control circuit.

19. A semiconductor integrated circuit device according to one of claims 16 to 18, wherein said substrate bias generating circuit is arranged in said second circuit block.

20. A semiconductor integrated circuit device according to one of claims 16 to 19, comprising said output fixing circuits for fixing levels of at least part of the signals which are inputted from said second circuit block to said first circuit block, when said substrate bias generating circuit changes the substrate bias voltages in such a way that thresholds of the transistors become high.

21. A semiconductor integrated circuit device having a first circuit block including transistors and a second circuit block for exchanging signals between said first circuit block and said second circuit block, said device comprising:

a substrate bias generating circuit for applying substrate bias voltages to a semiconductor substrate on which the transistors of said first circuit block are formed; and

a clock oscillation circuit for stopping a clock signal inputted to said first circuit block, when said substrate bias generating circuit changes the substrate bias voltages.

22. A semiconductor integrated circuit device according to claim 21, wherein said first circuit block is different in operation voltages from said second circuit block.

23. A semiconductor integrated circuit device according to claim 21 or 22, further comprising an output fixing circuit for fixing a level of an output signal of said clock oscillation circuit.

24. A semiconductor integrated circuit device according to one of claims 21 to 23, wherein said clock oscillation circuit is arranged in said second circuit block.

25. A semiconductor integrated circuit device according to one of claims 21 to 24, comprising said clock oscillation circuit for stopping the signal inputted to said first circuit block, when said substrate bias generating circuit changes the substrate bias voltages in such a way that the thresholds of the transistors become high.

26. A semiconductor integrated circuit device comprising:

a first circuit block including a logical circuit having MOS FETs, and driven by a first voltage; and

a second circuit block including an I/O circuit, a level holding circuit and a bias generating circuit, and driven by a second voltage,

wherein said bias generating circuit switches voltages applied to said main circuit in such a way that thresholds of the MOS FETs become high;

an output signal from said I/O circuit is inputted to said main circuit through an output fixing circuit; and

when switching the voltages by said bias generating circuit, said output fixing circuit fixes the output signal.

27. A semiconductor integrated circuit device according to claim 26, wherein a clock oscillation circuit is provided in said second circuit block, and when switching the voltages by said bias generating circuit, said output fixing circuit fixes the clock signal.

28. A semiconductor integrated circuit device according to claim 26 or 27, wherein a clock oscillation circuit is provided in said second circuit block, and a clock signal is supplied from said clock oscillation circuit to said main circuit, and when switching the voltages by said bias generating circuit and during the switching, the supply of the clock signal to said main circuit is stopped.

29. A semiconductor integrated circuit device according to one of claims 26 to 28, wherein said bias generating circuit switches the voltages supplied to said main circuit in such a way that thresholds of the MOS FETs of said main circuit become high, whereby said main circuit is switched from a normal operation mode over to a stand-by mode having the power consumption smaller than that of the normal operation mode.

30. A semiconductor integrated circuit device according to claim 29, wherein said main circuit includes a logical circuit, and in the greater part of the normal operation mode, said logical circuit functions.

31. A semiconductor integrated circuit device according to claim 30, wherein when switching said main circuit from the stand-by mode over to the normal mode by switching by said bias generating circuit the voltages supplied to said main circuit in such a way that the thresholds of the MOS FETs of said main circuit become low, said logical circuit starts functioning at a time point later than the time point of switching the voltages.

32. A semiconductor integrated circuit device according to claim 31, wherein after the voltages supplied to said main circuit have been stabilized, the operation of the MOS FETs of said main circuit is started.

33. A semiconductor integrated circuit device according to one of claims 26 to 32, wherein a substrate on which the MOS FETs are formed has a triple well structure in which a second semiconductor region of a second type is formed within a first semiconductor region of a first type, and a third semiconductor region of the first type is formed within said semiconductor region of the second type.

34. A processor comprising:

a processor main circuit for executing program instruction strings on a processor chip;

a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of said processor main circuit; and

an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in said processor main circuit, said substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, said substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of said processor main circuit to restart the operation.

35. A processor according to claim 34, wherein a semiconductor device of said processor chip has a triple well structure, and said processor main circuit is formed on a well region which is different from those of said substrate bias switching unit and said operation mode control unit.

36. A processor according to claim 34, wherein said operation mode control unit includes, as means for waiting, before restarting the operation of said processor main circuit when switching the biases, until the bias voltages switched thereto are stabilized, an on-chip timer for measuring a lapse of a time period required for stabilization of the biases.

37. A processor according to claim 34, wherein said operation mode control unit includes, as means for waiting, before restarting the operation of said processor main circuit when switching the biases, until the bias voltages switched thereto are stabilized, a sensor for detecting that the biases have been stabilized to predetermined voltages, respectively.

38. A processor according to claim 34, comprising:

said processor main circuit in which a semiconductor device of said processor chip has a triple well structure and is divided into a plurality of functional modules which are formed on different well regions, respectively;

said substrate bias switching unit for switching the substrate biases applied to the substrate of said functional modules; and

said operation mode control unit for controlling, in response to the execution of an instruction to make stand-by said one functional module or said plurality of functional modules in said processor main circuit, said substrate bias switching unit in such a way that the substrate biases of said one functional module or said plurality of functional modules are switched over to voltages for the stand-by mode, and for controlling, in response to a signal of the stand-by release of said one functional module or said plurality of functional modules from the outside or said processor main circuit, said substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for informing, after the bias voltages switched thereto have been stabilized, said processor main circuit of that the stand-by of said one functional module or said plurality of functional modules has been released.

39. A processor according to claim 34 or 37, further comprising:

means for switching dynamically the operation speed of said processor main circuit; and

said operation mode control unit for controlling, in response to the execution of an instruction to change the operation speed in said processor main circuit, said substrate bias switching unit in such a way that the substrate biases of said processor main circuit or said functional modules are switched over to voltages which are suitable for the operation frequency thereof, and for informing, after the bias voltages switched thereto have been stabilized, said processor main circuit of that the switching of the operation speed has been completed.

40. A processor according to claim 34 or 37, wherein said substrate bias switching unit is constituted by a substrate bias generating circuit for generating therein the voltages of the substrate biases.

41. A control method of controlling the power consumption of a semiconductor integrated circuit device including a plurality of element circuit blocks having transistors formed on a semiconductor substrate and operated on the basis of a clock signal, wherein a first mode in which all said element circuit blocks are operated on the basis of the clock-signal, a second mode in which the supply of the clock signal to at least one of said element circuit blocks is stopped, and a third mode in which the supply of the clock signal to all said element circuit blocks is stopped and also substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled so as to increase thresholds of the associated transistors are switched to be used.

42. A method of controlling a semiconductor integrated circuit device according to claim 41, wherein said element circuit blocks are included in a first circuit block, and the clock signal is produced from an oscillation circuit included in a second circuit block, and also the clock signal and information signals which are to be processed in said first circuit block are inputted from said second circuit block to said first circuit block.

43. A method of controlling a semiconductor integrated circuit device according to claim 42, wherein when switching the operation mode to said third mode, the clock signal and the information signals which are to be processed in said first circuit block are stopped from being inputted from said second circuit block to said first circuit block, and next, the substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled so as to increase the thresholds of the associated transistors.

44. A method of controlling a semiconductor integrated circuit device according to claim 43, wherein when switching the operation mode to said third mode, after the clock signal and the information signals which are to be processed in said first circuit block have been stopped from being inputted from said second circuit block to said first circuit block, and said device waits for a lapse of a predetermined time period using a timer, the substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled so as to increase the thresholds of the associated transistors.

45. A method of controlling a semiconductor integrated circuit device according to claim 42, wherein when switching the operation mode from said third mode to said first mode, the substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled so as to decrease the thresholds of the associated transistors, and next, the clock signal and the information signals which are to be processed in said first circuit block are started being inputted from said second circuit block to said first circuit block.

46. A method of controlling a semiconductor integrated circuit device according to claim 45, wherein when switching the operation mode from said third mode to said first mode, after the substrate biases of at least part of the transistors formed on the semiconductor substrate have been controlled so as to decrease the thresholds of the associated transistors, and said device waits for a lapse of a predetermined time period, the clock signal and the information signals which are to be processed in said first circuit block are started being inputted from said second circuit block to said first circuit block.

47. A method of controlling a semiconductor integrated circuit device according to claim 45, wherein when switching the operation mode from said third mode to said first mode, after the substrate biases of at least part of the transistors formed on the semiconductor substrate have been controlled so as to decrease the thresholds of the associated transistors, and the state of the thresholds of the associated transistors is confirmed, the clock signal and the information signals which are to be processed in said first circuit block are started being inputted from said second circuit block to said first circuit block.