METHOD FOR FORMING A LIQUID CRYSTAL DISPLAY PANEL

• US 20040159630A1
• Filed: 04/14/2003
• Published: 08/19/2004
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Chang, Lu-Kuen
• Granted Patent: US 7,060,195 B2
• Time in Patent Office: Days
• US Class Current: 216/24
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136254 Checking; Testing

Abstract

A plurality of scan lines and gate electrodes are formed on a pixel array area of a substrate, and a plurality of bottom pad electrodes are formed on a gate and a source pad area of the substrate. An insulating layer and a plurality of active layers are formed on the substrate. A plurality of signal lines, source/drain electrodes are formed on the pixel array area, and a plurality of top pad electrodes are formed on the gate and the source pad area. A circuit testing process is performed. A passivation layer having via holes is formed on the pixel array area, and a plurality of contact holes are formed in the gate and the source pad area. A patterned transparent conductive layer filling the via holes and the contact holes is formed on the substrate.

Claims

1. A method for forming a liquid crystal display panel (LCD panel), the method comprising:

providing a substrate, the substrate comprising a pixel array area, a gate pad area, and a source pad area positioned on a surface of the substrate and used for forming a plurality of pixels, a plurality of gate pads, and a plurality of source pads;

depositing a first metal layer on the substrate;

performing a first photo-etching-process (PEP) on the first metal layer to form a plurality of gate electrodes, a plurality of gate bottom pad electrodes, and a plurality of source bottom pad electrodes inside the pixel array area, the gate pad area, and the source pad area;

sequentially forming an insulating layer and a doped semiconductor layer on the substrate;

performing a second PEP on the doped semiconductor layer to form a plurality of active layers inside the pixel array area, and simultaneously remove portions of the doped semiconductor layer inside the gate pad area and the source pad area;

depositing a second metal layer on the substrate;

performing a third PEP on the second metal layer to form a plurality of source electrodes and a plurality of drain electrodes inside the pixel array area, and simultaneously form a plurality of gate top pad electrodes and a plurality of source top pad electrodes inside the gate pad area and the source pad area;

forming a passivation layer on the substrate;

performing a fourth PEP on the passivation layer to form a plurality of via holes inside the pixel array area, and simultaneously remove portions of the passivation layer inside the pixel array area;

forming a plurality of contact holes inside the gate pad area and the source pad area;

forming a transparent conductive layer on the substrate to fill the via holes inside the pixel array area and the contact holes inside the gate pad area and the source pad area; and

performing a fifth PEP to define patterns of the transparent conductive layer.

2. The method of claim 1 wherein the substrate comprises a glass substrate, a quartz substrate, or a plastic substrate.

3. The method of claim 1 wherein the gate pads are used to electrically connect to a gate driving integrated circuit (IC), and the source pads are used to electrically connect to a source driving IC.

4. The method of claim 1 further comprising forming a plurality of parallel scan lines on the substrate while performing the first PEP on the first metal layer, each scan line extending into the gate pad area and being electrically connected to a corresponding gate bottom pad electrode, and the scan lines being electrically connected with each other.

5. The method of claim 4 further comprising forming a plurality of signal lines on the substrate while performing the third PEP on the second metal layer, the plurality of signal lines being electrically connected with each other and being formed perpendicular to the scan lines, each signal line extending into the source pad area being overlapped partially with an underlying source bottom pad electrode and being electrically connected to a corresponding source top pad electrode, and each gate top pad electrode being overlapped partially with an underlying scan line.

6. The method of claim 5 wherein the scan lines and the signal lines are used to define the pixels, and each pixel comprises a bottom gate low temperature polysilicon silicon thin film transistor (LTPS TFT).

7. The method of claim 5 further comprising performing an electrical testing process for detecting whether the scan lines and the signal lines are broken or short-circuited.

8. The method of claim 7 wherein the electrical testing process is performed after performing the third PEP.

9. The method of claim 7 wherein the electrical testing process is performed after performing the fifth PEP.

10. The method of claim 7 further comprising performing a cutting process after performing the electrical testing process for removing an interconnection of the scan lines and the signal lines.

11. The method of claim 1 wherein the first metal layer and the second metal layer are both a single-metal structure, and the first metal layer and the second metal layer both comprise tungsten (W), chromium (Cr), copper (Cu), or molybdenum (Mo).

12. The method of claim 1 wherein the first metal layer and the second metal layer are both a double-metal structure, and the first metal layer and the second metal layer both comprise aluminum (Al) covering titanium (Al/Ti), aluminum covering chromium (Al/Cr), aluminum covering molybdenum (Al/Mo), aluminum neodymium covering molybdenum (AlNd/Mo), aluminum covering tungsten molybdenum (Al/MoW), or aluminum neodymium covering tungsten molybdenum (AlNd/MoW).

13. The method of claim 12 further comprising performing a wet etching process after performing the fourth PEP for removing an upper layer of the second metal layer under the via holes inside the pixel array area, and simultaneously removing an upper layer of the second metal layer of the gate top pad electrodes and the source top pad electrodes so as to prevent the upper layer of the second metal layer from electrically connecting to the transparent conductive layer formed later.

14. The method of claim 1 wherein the first metal layer and the second metal layer are both a triple-metal structure, and the first metal layer and the second metal layer both comprise molybdenum/aluminum/molybdenum (Mo/Al/Mo) or titanium/aluminum/titanium (Ti/Al/Ti).

15. The method of claim 1 wherein the insulating layer comprises silicon oxide (SiO_x), silicon nitride (SiN_y), or silicon oxynitride (SiON), the doped semiconductor layer comprises doped amorphous silicon or doped polysilicon, the passivation layer comprises silicon oxide or silicon nitride, and the transparent conductive layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

29. The method of claim 1 wherein the first metal layer and the second metal layer are both a triple-metal structure, and the first metal layer and the second metal layer both comprise molybdenum/aluminum/molybdenum (Mo/Al/Mo) or titanium/aluminum/titanium (Ti/Al/Ti).

16. A method for forming a liquid crystal display panel (LCD panel), the method comprising:

providing a substrate, the substrate comprising a pixel array area, a gate pad area, and a source pad area positioned on a surface of the substrate;

forming a plurality of parallel scan lines on the pixel array area of the substrate, and simultaneously forming a plurality of source bottom pad electrodes on the source pad area of the substrate, each scan line extending into the gate pad area and being electrically connected with each other, and portions of the scan lines positioned inside the gate pad area being used as a plurality of gate bottom pad electrodes;

forming an insulating layer on the substrate;

forming a plurality of signal lines perpendicular to the scan lines on the pixel array area of the substrate, and simultaneously forming a plurality of gate top pad electrodes partially overlapped with an underlying gate bottom pad electrode on the gate pad area of the substrate, each signal line extending into the source pad area and being electrically connected with each other, and portions of the signal lines positioned inside the source pad area being used as a plurality of source top pad electrodes and partially overlapped with an underlying source bottom pad electrode;

forming a plurality of contact holes inside the gate pad area and the source pad area; and

forming a patterned transparent conductive layer on the substrate.

17. The method of claim 16 wherein the substrate comprises a glass substrate, a quartz substrate, or a plastic substrate.

18. The method of claim 16 wherein the gate pad area is used to form a plurality of gate pads, and the gate pads are used to electrically connect to a gate driving integrated circuit (IC).

19. The method of claim 16 wherein the source pad is used to form a plurality of source pads, and the source pads are used to electrically connect to a source driving IC.

20. The method of claim 16 wherein the scan lines and the signal lines are used to define a plurality of pixels inside the pixel array area, and each pixel comprises a bottom gate low temperature polysilicon silicon thin film transistor (LTPS TFT).

21. The method of claim 20 wherein the method for forming the scan lines and the source bottom pad electrodes further comprises steps of:

depositing a first metal layer on the substrate; and

performing a first photo-etching-process (PEP) on the first metal layer to form the parallel scan lines inside the pixel array area of the substrate, and simultaneously form the source bottom pad electrodes inside the source pad area of the substrate, each scan line extending into the gate pad area and being electrically connected with each other.

22. The method of claim 21 further comprising forming a gate electrode inside each pixel while performing the first PEP on the first metal layer.

23. The method of claim 22 further comprising forming a patterned doped semiconductor layer on the insulating layer after forming the insulating layer, wherein the patterned doped semiconductor layer comprises doped amorphous silicon or doped polysilicon.

24. The method of claim 23 wherein the method for forming the patterned doped semiconductor layer further comprises steps of:

forming a doped semiconductor layer on the insulating layer; and

performing a second PEP on the doped semiconductor layer to form a plurality of active layers inside the pixel array area of the substrate, and simultaneously remove portions of the doped semiconductor layer positioned inside the gate pad area and the source pad area of the substrate.

25. The method of claim 24 wherein the method for forming the signal lines and the gate top pad electrodes further comprises steps of:

depositing a second metal layer on the substrate; and

performing a third PEP on the second metal layer to form the signal lines perpendicularly to the scan lines inside the pixel array area of the substrate, and simultaneously form the gate top pad electrodes inside the gate pad area of the substrate, each signal line extending into the source pad area and being electrically connected with each other, each gate top pad electrode being partially overlapped with an underlying gate bottom pad electrode, and each source top pad electrode being partially overlapped with an underlying source bottom pad electrode.

26. The method of claim 25 wherein the first metal layer and the second metal layer are both a single-metal structure, and the first metal layer and the second metal layer both comprise tungsten (W), chromium (Cr), copper (Cu), or molybdenum (Mo).

27. The method of claim 25 wherein the first metal layer and the second metal layer are both a double-metal structure, and the first metal layer and the second metal layer both comprise aluminum (Al) covering titanium (Al/Ti), aluminum covering chromium (Al/Cr), aluminum covering molybdenum (Al/Mo), aluminum neodymium covering molybdenum (AlNd/Mo), aluminum covering tungsten molybdenum (Al/MoW), or aluminum neodymium covering tungsten molybdenum (AlNd/MoW).

28. The method of claim 27 further comprising performing a wet etching process before forming the patterned transparent conductive layer for removing an upper layer of the second metal layer of the gate top pad electrodes and the source top pad electrodes so as to prevent the upper layer of the second metal layer of the gate top pad electrodes and the source top pad electrodes from electrically connecting to the patterned transparent conductive layer formed later.

30. The method of claim 25 further comprising forming a passivation layer on the substrate before removing the insulating layer, the passivation layer comprising silicon oxide or silicon nitride.

31. The method of claim 30 wherein the method for forming the passivation layer further comprises steps of:

forming a passivation layer on the substrate; and

performing a fourth PEP on the passivation layer to form a plurality of via holes inside the pixel array area of the substrate, and simultaneously remove portions of the passivation layer outside the pixel array area of the substrate.

32. The method of claim 31 wherein the method for forming the patterned transparent conductive layer further comprises steps of:

forming a transparent conductive layer on the substrate to fill the via holes inside the pixel array area and the contact holes inside the gate pad area and the source pad area; and

performing a fifth PEP to define patterns of the transparent conductive layer for forming the patterned transparent conductive layer.

33. The method of claim 16 wherein the insulating layer comprises silicon oxide (SiO_x), silicon nitride (SiN_y), or silicon oxynitride (SiON), and the patterned transparent conductive layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

34. The method of claim 16 further comprising performing an electrical testing process for detecting if the scan lines and the signal lines are broken or short-circuited.

35. The method of claim 34 wherein the electrical testing process is performed after performing the third PEP.

36. The method of claim 34 wherein the electrical testing process is performed after performing the fifth PEP.

37. The method of claim 34 further comprising performing a cutting process after the electrical testing process for removing an interconnection of the scan lines and the signals.