Analog delay locked loop with tracking analog-digital converter

• US 20040160250A1
• Filed: 12/31/2003
• Published: 08/19/2004
• Est. Priority Date: 01/09/2003
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Se-Jun, Hong, Sang-Hoon, Ko, Jae-Bum
• Granted Patent: US 6,987,409 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03M 1/48 Servo-type converters

Abstract

An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.

Claims

1. An analog DLL which buffers an external clock signal and uses the buffered clock signal as a reference clock signal, comprising:

a delay model for modeling delay time for buffering the external clock signal;

a phase comparator for comparing an phase of the reference clock signal with an phase of an outputted signal from the delay model;

a charge pump for pumping charges in response to an outputted signal from the phase comparator;

a loop filter for generating a reference voltage which is determined by a quantity of charges inputted from the charge pump;

a voltage control delay line which delays the reference clock signal for a predetermined time, and outputs the delayed clock signal to the delay model, where the predetermined time is determined by the reference voltage; and

a tracking digital-analog converter which converts the reference voltage to a digital value, and stores the digital value for keeping the reference voltage safely, and outputs a tracking voltage which corresponds to the digital value to the loop filter.

2. The analog DLL as recited in claim 1, wherein the tracking voltage is outputted to the loop filter during a standby mode.

3. The analog DLL as recited in claim 2, wherein the loop filter includes a capacitor for storing the reference voltage.

4. The analog DLL as recited in claim 2, wherein the tracking digital-analog converter includes:

a voltage comparator for comparing the reference voltage with the tracking voltage;

a counting means for counting in response to an outputted signal from the voltage comparator, and for outputting an counting signal;

a register for storing a digital value which corresponds to the counting signal; and

an digital-analog converting means for generating a voltage which corresponds to the digital value, and for outputting the voltage as the tracking voltage.

5. The analog DLL as recited in claim 4, wherein the digital-analog converting means includes:

a main digital-analog converter which generates a first tracking voltage for a high speed tracking, where the first tracking voltage corresponds to predetermined upper bits of the digital value; and

a sub digital-analog converter which generates a second tracking voltage for correcting the first tracking voltage to be equal to the reference voltage, where the second tracking voltage corresponds to all the bits, except the predetermined upper bits, of the digital value.

6. The analog DLL as recited in claim 5, wherein the digital-analog converting means is provided with a binary-thermometer converter which converts the predetermined upper bits to a thermometer code, and outputs the converted thermometer code to the main digital-analog converter, where the main digital-analog converter is segment typed.

7. The analog DLL as recited in claim 4, a unit gain buffer is included for buffering an outputted signal from the main digital-analog converter and the sub digital-analog converter, and for outputting the buffered signal as the tracking voltage.

8. The analog DLL as recited in claim 7, a switch is included for transferring the tracking voltage outputted from the unit gain buffer to the loop filter.

9. The analog DLL as recited in claim 3, wherein the reference voltage is determined by charges pumped by the charge pump when the analog DLL is locked.

10. The analog DLL as recited in claim 7, wherein all the blocks except the register, the digital-analog converting means and the unit gain buffer become disabled during the standby mode.

11. An analog phase locked loop (PLL) which buffers an external clock signal and uses the buffered clock signal as a reference clock signal, comprising:

a delay model for modeling delay time for buffering the external clock signal;

a phase comparator for comparing an phase of the reference clock signal with an phase of an outputted signal from the delay model;

a charge pump for pumping charges in response to an outputted signal from the phase comparator;

a loop filter for generating a reference voltage which is determined by a quantity of charges inputted from the charge pump;

a voltage control oscillator which modulates a frequency of the reference clock signal, and outputs the modulated signal to the delay model; and

a tracking digital-analog converter which converts the reference voltage to a digital value, and stores the digital value for keeping the reference voltage safely, and outputs a tracking voltage which corresponds to the digital value to the loop filter.

12. The analog PLL as recited in claim 11, wherein the tracking voltage is outputted to the loop filter during a standby mode.

13. The analog PLL as recited in claim 12, wherein the loop filter includes a capacitor for storing the reference voltage.

14. The analog PLL as recited in claim 12, wherein the tracking digital-analog converter includes:

a voltage comparator for comparing the reference voltage with the tracking voltage;

a counting means for counting in response to an outputted signal from the voltage comparator, and for outputting an counting signal;

a register for storing a digital value which corresponds to the counting signal; and

an digital-analog converting means for generating a voltage which corresponds to the digital value, and for outputting the voltage as the tracking voltage.

15. The analog DLL as recited in claim 14, wherein the digital-analog converting means includes:

a main digital-analog converter which generates a first tracking voltage for a high speed tracking, where the first tracking voltage corresponds to predetermined upper bits of the digital value; and

a sub digital-analog converter which generates a second tracking voltage for correcting the first tracking voltage to be equal to the reference voltage, where the second tracking voltage corresponds to all the bits, except the predetermined upper bits, of the digital value.

16. The analog PLL as recited in claim 15, wherein the digital-analog converting means is provided with a binary-thermometer converter which converts the predetermined upper bits to a thermometer code, and outputs the converted thermometer code to the main digital-analog converter, where the main digital-analog converter is segment typed.

17. The analog PLL as recited in claim 14, a unit gain buffer is included for buffering an outputted signal from the main digital-analog converter and the sub digital-analog converter, and for outputting the buffered signal as the tracking voltage.

18. The analog PLL as recited in claim 17, a switch is included for transferring the tracking voltage outputted from the unit gain buffer to the loop filter.

19. The analog PLL as recited in claim 13, wherein the reference voltage is determined by charges pumped by the charge pump when the analog PLL is locked.

20. The analog PLL as recited in claim 17, wherein all the blocks except the register, the digital-analog converting means and the unit gain buffer become disabled during the standby mode.