MEMORY HAVING VARIABLE REFRESH CONTROL AND METHOD THEREFOR

• US 20040160838A1
• Filed: 02/19/2003
• Published: 08/19/2004
• Est. Priority Date: 02/19/2003
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pelley, Perry H., Burgan, John M.
• Granted Patent: US 6,781,908 B1
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Claims

1. A memory comprising:

a plurality of memory cells that require periodic refreshing to maintain stored data;

a charge pump, coupled to the plurality of memory cells, for providing a substrate bias;

a voltage regulator, coupled to the charge pump, for providing a pump enable signal for controlling a voltage level of the substrate bias;

a refresh counter having an input terminal coupled to the voltage regulator for receiving the pump enable signal, and in response, providing a refresh timing signal; and

a refresh control circuit, coupled to receive the refresh timing signal, and in response, controlling refresh operations of the plurality of memory cells.

2. The memory of claim 1, wherein the plurality of memory cells and the plurality of test memory cells are dynamic random access memory (DRAM) cells.

3. The memory of claim 1, wherein a charge retention ability of the plurality of memory cells is measured during wafer probe testing.

4. The memory of claim 1, wherein a charge retention ability of the plurality of memory cells is measured during board level burn-in.

5. The memory of claim 1, wherein a refresh rate of the plurality of memory cells is adjusted by the refresh counter in response to the pump enable signal.

6. The memory of claim 1, wherein a counter value of the refresh counter is adjustable.

7. The memory of claim 6, wherein the counter value of the refresh counter is adjusted using a programmable fuse circuit.

8. The memory of claim 7, wherein the memory is a portion of an integrated circuit die, a plurality of the integrated circuit die included on a semiconductor wafer, and wherein the programmable fuse circuit is used during wafer probe testing of the semiconductor wafer to adjust the count rate of the refresh counter.

9. The memory of claim 8, further comprising a built-in self test (BIST) circuit for scanning test data into and out of the plurality of memory cells during the wafer probe testing.

10. The memory of claim 9, wherein during wafer probe testing of the semiconductor wafer, a charge retention ability of the plurality of memory cells is measured.

11. The memory of claim 10, wherein the plurality of integrated circuit die are compared according to the measured charge retention ability of each of the plurality of integrated circuit die.

12. A memory comprising:

a plurality of memory cells that require periodic refreshing to maintain stored data;

a charge pump for providing a substrate bias to the plurality of memory cells;

a voltage regulator, coupled to the charge pump, for providing a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits;

a refresh control circuit for controlling refresh operations of the plurality of memory cells; and

a refresh counter having an input terminal coupled to the voltage regulator for receiving the pump enable signal, and in response, providing a refresh timing signal to the refresh control circuit to control a refresh rate of the plurality of memory cells;

wherein the refresh rate is adjusted by the refresh counter in response to the voltage regulator asserting the pump enable signal.

13. The memory of claim 12, wherein the plurality of memory cells and the plurality of test memory cells are dynamic random access memory (DRAM) cells.

14. The memory of claim 12, wherein the refresh rate varies with temperature.

15. The memory of claim 12, wherein a counter value of the refresh counter is adjusted using a programmable fuse circuit.

16. The memory of claim 15, wherein the memory is a portion of a packaged integrated circuit die, and wherein the programmable fuse circuit is used during board level testing of the packaged integrated circuit die to adjust the counter value.

17. The memory of claim 15, wherein the memory is a portion of an integrated circuit die, a plurality of the integrated circuit die are included on a semiconductor wafer, and wherein the programmable fuse circuit is used during wafer probe testing of the semiconductor wafer to adjust the counter value.

18. The memory of claim 17, further comprising a built-in self test (BIST) circuit for scanning test data into and out of the plurality of memory cells during the wafer probe testing.

19. The memory of claim 18, wherein during wafer probe testing of the semiconductor wafer, a charge retention ability of the plurality of memory cells is measured.

20. The memory of claim 19, wherein the plurality of integrated circuit die are compared according to the measured charge retention ability of each of the plurality of integrated circuit die.

21. A method for testing a plurality of integrated circuit memories, each of the integrated circuit memories having a plurality of memory cells that require periodic refreshing to maintain stored data, the method comprising the steps of:

providing a semiconductor wafer having the plurality of the integrated circuit memories, each of the plurality of integrated circuit memories having a refresh counter for providing a refresh timing signal to the refresh control circuit to control a refresh rate of the plurality of memory cells;

providing a programmable fuse circuit coupled to the refresh control circuit on each of the plurality of integrated circuit memories;

providing a built-in self test (BIST) circuit on each of the plurality of integrated circuits for scanning test data into and out of the plurality of memory cells on each of the plurality of integrated circuit memories;

providing a plurality of wafer test pads coupled to the BIST circuits on the semiconductor wafer;

contacting the wafer test pads with wafer probe needles;

measuring a charge retention ability of the plurality of memory cells on each of the plurality of integrated circuits;

analyzing the charge retention ability of the plurality of memory cells on each of the plurality of integrated circuits to determine a plurality of refresh rates, a refresh rate corresponding to each of the plurality of integrated circuits; and

programming each of the programmable fuse circuits of the plurality of integrated circuits with its corresponding refresh rate.

22. The method of claim 21, further comprising the step of adjusting a test temperature of the wafer.