Semiconductor memory device suppressing peak current

• US 20040160842A1
• Filed: 09/05/2003
• Published: 08/19/2004
• Est. Priority Date: 02/19/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Fukiage, Takahiko
• Granted Patent: US 6,801,460 B2
• Time in Patent Office: Days
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

In a semiconductor memory device including a plurality of memory chips, the plurality of memory chips are divided into first and second groups that are operated in parallel with each other at the time of a data read. Timings of activating sense amplifiers belonging to the first and second groups are made different from each other. Accordingly, the maximum value of peak current generated when the sense amplifiers are activated at the time of a data read is reduced by half in the semiconductor memory device as a whole. As the peak current is suppressed, the data reading operation can be executed stably.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory chips formed on one board, each executing data storage independently, and operating in parallel a data read operation;

wherein

said plurality of memory chips are divided into first and second groups,

each of said memory chips comprises

a memory array having a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of bit lines corresponding to the memory cell columns,

a precharge circuit activated before data reading to precharge said bit lines to a prescribed voltage,

a sense amplifier activated at the time of said data reading to amplify data stored in said plurality of memory cells, and

a preamplifier activated at the time of said data reading to further amplify the data that has been amplified by said sense amplifier,

an output buffer activated at the time of said data reading to output said stored data amplified by said preamplifier, and

an activation signal generating unit generating an activation signal based on a command input for activating at least one of said precharge circuit, said sense amplifier, said preamplifier, and said output buffer,

said activation signal generating unit includes

a common activation signal generating circuit generating a common activation signal based on said command input at the same timing independent of which group the memory chip belongs to,

a group determination circuit generating a group determination signal for determining which group the memory chip belongs to, and

a timing control circuit generating said activation signal based on said group determination signal and said common activation signal at the timing corresponding to said belonging group.

2. The semiconductor memory device according to claim 1, wherein

said activation signal generating unit includes

a command generating circuit designating a prescribed operation in each of said memory chips in accordance with said command input,

a sense amplifier activation signal generating unit generating a signal activating said sense amplifier in response to a signal output from said command generating circuit,

a preamplifier activation signal generating unit generating a signal activating said preamplifier in response to a signal output from said command generating circuit,

an output buffer activation signal generating unit generating a signal activating said output buffer in response to a signal output from said command generating circuit, and

a precharge circuit activation signal generating unit generating a signal activating said precharge circuit in response to a signal output from said command generating circuit,

each of said sense amplifier activation signal generating unit, said preamplifier activation signal generating unit, said output buffer activation signal generating unit and said precharge circuit activation signal generating unit has said common activation signal generating circuit, said group determination circuit and said timing control circuit, and outputs the corresponding activation signal.

3. The semiconductor memory device according to claim 1, wherein

said group determination circuit includes an external pin and a buffer circuit, and generates said group determination signal in response to an input signal input from said external pin.

4. The semiconductor memory device according to claim 1, wherein

said group determination circuit includes a fuse element, and generates said group determination signal in accordance with connection/disconnection of said fuse element.