Line drivers that use minimal metal layers
First Claim
Patent Images
1. A driver set for a cross point memory array comprising:
- a semiconductor substrate with an active surface in the x-direction and y-direction directions;
a plurality of line driver groups formed on the active surface of the substrate and stacked in the y-direction, each line driver group having transistors in various positions;
a plurality of y-direction lines on a first fabrication layer above the active surface of the semiconductor substrate, each y-direction line electrically connecting the transistors of a line driver group to transistors of other line driver groups that share the same relative position;
a plurality of first x-direction lines on a second fabrication layer above the active surface of the semiconductor substrate that electrically connects the transistors of a line driver group to each other;
a plurality of second x-direction lines on the second fabrication layer, each second x-direction line electrically connecting the line drivers in each line driver group;
a plurality of third x-direction lines on the second fabrication layer, each third x-direction line electrically connected to a single line driver.
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Abstract
Line drivers that use minimal metal layers. Line driver connections typically need to be made to various other peripheral circuits. Although multiple metal layers could be used to make all the necessary connections, it is desirable to use the fewest metal layers possible. By keeping all y-direction lines on a first layer, and most of the x-direction lines on a second layer, only two metal layers are required. Additionally, an array cut could be used that allows line drivers to reach upper conductive array lines.
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Citations
26 Claims
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1. A driver set for a cross point memory array comprising:
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a semiconductor substrate with an active surface in the x-direction and y-direction directions;
a plurality of line driver groups formed on the active surface of the substrate and stacked in the y-direction, each line driver group having transistors in various positions;
a plurality of y-direction lines on a first fabrication layer above the active surface of the semiconductor substrate, each y-direction line electrically connecting the transistors of a line driver group to transistors of other line driver groups that share the same relative position;
a plurality of first x-direction lines on a second fabrication layer above the active surface of the semiconductor substrate that electrically connects the transistors of a line driver group to each other;
a plurality of second x-direction lines on the second fabrication layer, each second x-direction line electrically connecting the line drivers in each line driver group;
a plurality of third x-direction lines on the second fabrication layer, each third x-direction line electrically connected to a single line driver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A driver set for a cross point memory array comprising:
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a plurality of line driver groups that are electrically connected to a reference voltage;
a primary decoder;
a secondary decoder; and
a memory array;
wherein the electrical connections are achieved in two metallization layers. - View Dependent Claims (11)
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12. A driver set comprising:
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a plurality of line driver groups that are stacked in a first direction, each line driver group having a plurality of line driver stages, each line driver stage having two line drivers such that the first line driver has transistors that share a common node with transistors of the second line driver, wherein each transistor in each line driver group has a relative position;
a first metal layer that electrically connects all the transistors in the same relative position to each other with conductive lines in the first direction, and provides an extension for one line driver stage in a second direction, the second direction being orthogonal to the first direction; and
a second metal layer that electrically connects all the transistors to a memory array, and electrically connects all the line driver stages in each line driver group, whereby the electrical connection in the one line driver stage is made via the extension.
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13. A re-writable cross point memory array comprising:
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a semiconductor substrate with an active surface in the x and y directions;
a plurality of line driver groups formed on the active surface of the substrate and stacked in the x and y directions, each line driver group having transistors in various positions and no more than two metallization layers;
one or two x-direction conductive layers that include conductive array lines, the conductive array lines electrically connected to the x direction line driver groups; and
one y-direction conductive layer that include conductive array lines, the conductive array lines electrically connected to the y direction line driver groups; and
memory plugs. - View Dependent Claims (14, 16)
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15. A re-writable cross point memory array comprising:
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a semiconductor substrate with an active surface in the x and y directions;
a plurality of line driver groups formed on the active surface of the substrate and stacked in the x and y directions, each line driver group having transistors in various positions, and no more than three metallization layers;
three x-direction conductive layers that include conductive array lines;
two y-direction conductive layer that include conductive array lines; and
memory plugs.
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17. A cross point memory array comprising:
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at least one x-direction conductive layers that include conductive array lines that terminate at line ends;
at least one y-direction conductive layer that include conductive array lines;
memory plugs; and
a plurality of x-direction line drivers that drive x-direction conductive array lines;
wherein at least some x-direction line drivers connect with the x-direction conductive lines at a location other than the line ends. - View Dependent Claims (18)
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19. A cross point memory array comprising:
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memory plugs having tops and bottoms;
a plurality of y-direction conductive array lines in electrical contact with the tops of the memory plugs;
a plurality of x-direction conductive array lines in electrical contact with the bottoms of the memory plugs;
wherein the plurality of x-direction conductive array lines includes an array cut that is where two contiguous x-direction conductive array lines are spaced further apart than other contiguous x-direction conductive array lines. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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Specification