Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects

• US 20040162716A1
• Filed: 02/13/2003
• Published: 08/19/2004
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Dorfman, Barry Lee, Soreff, Jeffrey Paul, Rosser, Thomas Edward
• Granted Patent: US 7,552,040 B2
• Time in Patent Office: Days
• US Class Current: 703/15
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

Claims

1. A method for modeling the behavior of a logical circuit block, the method comprising:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block; and

second calculating a delay time of said logical circuit block as a second mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to said output of said logical circuit block, wherein a deviation of said transition time and a deviation of said delay time due to voltage non-linearities of said transistor gate capacitance is modeled by said first and second calculating.

2. The method of claim 1, wherein said first and second mathematical function are further functions of a static load capacitance in addition to said transistor gate capacitance, whereby both linear and non-linear capacitances connected to said output of said logical circuit block are modeled in said first and second calculating.

3. The method of claim 2, wherein said first and second mathematical functions are functions of a total capacitance and a ratio of said transistor gate capacitance to a total capacitance connected to said output of said logical circuit block, and wherein said method further comprises:

first computing said transistor gate capacitance by multiplying said total capacitance by said ratio; and

second computing said static capacitance by subtracting said transistor gate capacitance from said total capacitance.

4. The method of claim 1, further comprising:

first computing a first capacitance for modeling one or more N-channel devices connected to said output of said logical circuit block;

second computing a second capacitance for modeling one or more P-channel devices connected to said output of said logical circuit block, and wherein said first and second mathematical functions are further functions of said first and second capacitances, whereby loading effects of said N-channel and P-channel devices are separately accounted for in said first and second calculating.

5. The method of claim 4, further comprising:

first totaling a first plurality of gate capacitances of said N-channel devices to determine said first capacitance; and

second totaling a second plurality of gate capacitances of said P-channel devices to determine said first capacitance.

6. The method of claim 1, wherein said first and second mathematical functions are further functions of a ratio of a first capacitance of one or more N-channel devices connected to said output said logical circuit block and a second capacitance of one or more P-channel devices connected to said output of said logical circuit block.

7. A workstation computer system including a memory for storing program instructions and data, and a processor for executing said program instructions, and wherein said program instructions comprise program instructions for:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block, and

second calculating a delay time of said logical circuit block as a second mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to said output of said logical circuit block, wherein a deviation of said transition time and a deviation of said delay time due to voltage non-linearities of said transistor gate capacitance is modeled by said first and second calculating.

8. The workstation computer system of claim 7, wherein said first and second mathematical function are further functions of a static load capacitance in addition to said transistor gate capacitance, whereby both linear and non-linear capacitances connected to said output of said logical circuit block are modeled in said first and second calculating.

9. The workstation computer system of claim 8, wherein said first and second mathematical functions are functions of a total capacitance and a ratio of said transistor gate capacitance to a total capacitance connected to said output of said logical circuit block, and wherein program instructions further comprise program instructions for:

first computing said transistor gate capacitance by multiplying said total capacitance by said ratio; and

second computing said static capacitance by subtracting said transistor gate capacitance from said total capacitance.

10. The workstation computer system of claim 7, wherein said program instructions further comprise program instructions for:

first computing a first capacitance for modeling one or more N-channel devices connected to said output of said logical circuit block;

second computing a second capacitance for modeling one or more P-channel devices connected to said output of said logical circuit block, and wherein said first and second mathematical functions are further functions of said first and second capacitances, whereby loading effects of said N-channel and P-channel devices are separately accounted for in said first- and second calculating.

11. The workstation computer system of claim 10, wherein said program instructions further comprise program instructions for:

first totaling a first plurality of gate capacitances of said N-channel devices to determine said first capacitance; and

second totaling a second plurality of gate capacitances of said P-channel devices to determine said first capacitance.

12. The workstation computer system of claim 7, wherein said first and second mathematical functions are further functions of a ratio of a first capacitance of one or more N-channel devices connected to said output of said logical circuit block and a second capacitance of one or more P-channel devices connected to said output of said logical circuit block.

13. A computer program product comprising signal-bearing media encoding program instructions and data for execution on a general-purpose computer system, wherein said program instructions comprise program instructions for:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block, and

second calculating a delay time of said logical circuit block as a second mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to said output of said logical circuit block, wherein a deviation of said transition time and a deviation of said delay time due to voltage non-linearities of said transistor gate capacitance is modeled by said first and second calculating.

14. The computer program product of claim 13, wherein said first and second mathematical function are further functions of a static load capacitance in addition to said transistor gate capacitance, whereby both linear and non-linear capacitances connected to said output of said logical circuit block are modeled in said first and second calculating.

15. The computer program product of claim 14, wherein said first and second mathematical functions are functions of a total capacitance and a ratio of said transistor gate capacitance to a total capacitance connected to said output of said logical circuit block, and wherein program instructions further comprise program instructions for:

first computing said transistor gate capacitance by multiplying said total capacitance by said ratio; and

second computing said static capacitance by subtracting said transistor gate capacitance from said total capacitance.

16. The computer program product of claim 13, wherein said program instructions further comprise program instructions for:

first computing a first capacitance for modeling one or more N-channel devices connected to said output of said logical circuit block;

second computing a second capacitance for modeling one or more P-channel devices connected to said output of said logical circuit block, and wherein said first and second mathematical functions are further functions of said first and second capacitances, whereby loading effects of said N-channel and P-channel devices are separately accounted for in said first and second calculating.

17. The computer program product of claim 16, wherein said program instructions further comprise program instructions for:

first totaling a first plurality of gate capacitances of said N-channel devices to determine said first capacitance; and

second totaling a second plurality of gate capacitances of said P-channel devices to determine said first capacitance.

18. The computer program product of claim 15, wherein said first and second mathematical functions are further functions of a ratio of a first capacitance of one or more N-channel devices connected to said output of said logical circuit block and a second capacitance of one or more P-channel devices connected to said output of said logical circuit block.

19. A method for determining coefficients for a logical circuit block model, comprising:

measuring a gate current conducted from a logical circuit block output into a loading circuit transistor gate; and

simulating a shunt current conducted from said logical circuit block output to a return path, wherein the magnitude of the shunt current is set to a value functionally dependent on the measured gate current, whereby effects of said transistor gate on logical circuit block performance may be measured without adjusting transistor sizes.

20. The method of claim 19, further comprising second simulating an independently variable shunt capacitance connected from said logical circuit block output to a return path, whereby effects of a static loading capacitance on said logical circuit block performance is simulated.