System and method for evaluating signal coupling between vias in a package design

• US 20040163056A1
• Filed: 02/19/2003
• Published: 08/19/2004
• Est. Priority Date: 02/19/2003
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Frank, Mark D., Nelson, Jerimy, Modauer, Peter Shaw
• Application Number:
  US10/368,776
• Publication Number:
  US 20040163056A1
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method is provided for evaluating via signal coupling in an electronic design (e.g., a package design). In the method, one or more via signal coupling rules are formulated. One or more via pairs designed to carry differential signals are then processed to determine whether the inter-via spacing between the via pairs violates the via signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated via signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Claims

1. A method for evaluating via signal coupling in an electronic design, comprising the steps of:

formulating one or more via signal coupling rules;

processing the electronic design to determine whether the via signal coupling between via pairs of the electronic design violate the via signal coupling rules; and

generating an indicator associated with the electronic design to identify violated via signal coupling rules.

2. A method of claim 1, the step of processing comprising the step of processing one signal net pair of the electronic design for violation of the via signal coupling rules.

3. A method of claim 1, the electronic design comprising a package design, the step of formulating comprising the step of formulating one or more group via signal coupling rules for a group of signal nets of the package design, wherein the step of processing comprises the step of processing the group of signal nets to determine whether inter-via spacings between differential signal net pairs of the group violate the group via signal coupling rules.

4. A method of claim 3, the step of generating comprising the step of generating at least one DRC for one or more violations of the group via signal coupling rules.

5. A method of claim 1, wherein the step of formulating one or more via signal coupling rules comprises defining an inter-via spacing dimension to ensure signal coupling between the via pairs, the step of processing comprising the step of determining whether the inter-via spacing of the via pairs differs from the inter-via spacing dimension.

6. A method of claim 5, the inter-via dimension comprising approximately 200 microns.

7. A method of claim 5, step of formulating comprising the step of defining a tolerance about the dimension.

8. A method of claim 7, the tolerance comprising one of (a) 10% deviation from the dimension and (2) 20 microns deviation from the dimension.

9. A method of claim 7, the step of processing comprising the step of determining whether the inter-via spacing of the via pairs differs from the inter-via spacing dimension, plus or minus the tolerance.

10. A method of claim 1, the step of generating an indicator comprising the step of graphically depicting a DRC on a graphical user interface illustrating the electronic design.

11. A method of claim 1, the step of processing comprising the step of determining a spacing between each of the via pairs.

12. A method of claim 1, the electronic design comprising a package design, the via signal coupling rules defining via signal coupling for a group of signal nets of the package design.

13. A method of claim 1, the step of generating an indicator comprising generating a report summarizing violations of the via signal coupling rules.

14. A software product comprising instructions, stored on computer-readable media, wherein the instructions, when executed by a computer, perform steps for evaluating via signal coupling in an electronic design, comprising:

determining inter-via spacing between at least one via pair of the electronic design;

comparing the spacing to one or more via signal coupling rules; and

generating an indicator associated with the electronic design to identify violations of the via signal coupling rules.

15. The software product of claim 14, further comprising formulating one or more of the via signal coupling rules.

16. The software product of claim 14, further comprising determining whether one signal net in a group of signal nets has any via pairs that violate the via signal coupling rules.

17. The software product of claim 14, further comprising generating a report summarizing violations of the via signal coupling rules.

18. The software product of claim 14, the step of comparing comprising the step of comparing the spacing to a desired inter-via dimension set forth in the via signal coupling rules.

19. The software product of claim 18, the step of comparing comprising the step of comparing the spacing to the desired inter-via dimension with a tolerance defined in the via signal coupling rules.

20. The software product of claim 14, further comprising responding to designer inputs to scope the step of determining inter-via spacing of the at least one via pair.

21. A system for evaluating via signal coupling in an electronic design, comprising:

means for formulating one or more via signal coupling rules;

means for processing the electronic design to determine whether the via signal coupling between via pairs of the electronic design violate the via signal coupling rules;

an

means for generating an indicator associated with the electronic design to identify violated via signal coupling rules.