Programmable event driven yield mechanism which may activate other threads

• US 20040163083A1
• Filed: 02/19/2003
• Published: 08/19/2004
• Est. Priority Date: 02/19/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zou, Xiang, Shen, John, Wang, Hong, Hammarlund, Per, Tian, Xinmin, Wang, Perry, Girkar, Milind, Desai, Piyush
• Granted Patent: US 7,487,502 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Claims

1. An apparatus comprising:

execution resources to execute a plurality of instructions;

a monitor to detect a low progress indicating condition of said execution resources, said monitor to selectively disrupt processing of at least one program by transferring to a handler in response to detecting said low progress indicating condition.

2. The apparatus of claim 1 wherein the monitor is enabled to detect the low progress indicating condition by an instruction, wherein the low progress indicating condition is to be detected subsequent to completion of execution of the instruction.

3. The apparatus of claim 1 wherein said low progress indicating condition is a count of microarchitectural events.

4. The apparatus of claim 1 wherein said monitor is one of a plurality of monitors and wherein said low progress indicating condition comprises one or more programmable counts being reached by one or more of the plurality of monitors.

5. The apparatus of claim 4 wherein said plurality of monitors are processor performance monitors that are also readable by a processor instruction.

6. The apparatus of claim 1 wherein said apparatus is a processor and wherein said low progress indicating condition comprises a programmable combination of processor-internal events.

7. The apparatus of claim 1 wherein said monitor is to cause an imprecise control flow change tied to one or more processor events rather than an instruction-execution boundary.

8. The apparatus of claim 4 wherein one or more of said plurality of monitors is to cause an asynchronous control flow change tied to one or more processor events rather execution of a single instruction.

9. The apparatus of claim 1 wherein said monitor is one of a plurality of monitors, the apparatus further comprising:

an event schema vector storage location to store an event schema vector comprising a plurality of bits, each bit corresponding to one ore more conditions associated with said plurality of monitors;

an event schema vector mask storage location to store an event schema vector mask comprising a second plurality of bits to indicate whether corresponding bits of the event schema vector are masked.

10. The apparatus of claim 9 wherein each of the plurality of bits of the event schema vector represents an event all of which are to occur to indicate a composite event and disrupt processing unless masked.

11. The apparatus of claim 9 wherein each of the plurality of bits of the event schema vector represent one or more events which disrupts processing unless masked.

12. The apparatus of claim 11 further comprising:

a memory to store an event descriptor table.

13. The apparatus of claim 1 wherein said handler is an event handler routine stored in a computer readable medium.

14. The apparatus of claim 13 wherein said execution resources comprise multithreaded execution logic capable of executing a plurality of threads, and wherein said event handler routine, if executed, is to launch a helper thread.

15. The apparatus of claim 14 wherein said helper thread and a first thread executing when said low progress indicating condition is detected are executed concurrently.

16. The apparatus of claim 15 wherein said helper thread sets a new low progress indicating condition to trigger another helper thread.

17. The apparatus of claim 1 wherein said monitor is context sensitive.

18. The apparatus of claim 1 wherein said monitor is programmable by a user program at a low privilege level to activate said handler in response to conditions at least partially caused by said user program.

19. An apparatus comprising:

execution logic to execute a program;

event detection logic to execute an event handler in response a program-definable condition of the execution logic during execution of the program.

20. The apparatus of claim 19 further comprising:

an event enablement indicator, the event enablement indicator being programmable to indicate whether to presently recognize an event.

21. The apparatus of claim 19 wherein said event detection logic is programmable by a program operative at a user privilege level.

22. The apparatus of claim 21 wherein said event detection logic is context sensitive.

23. The apparatus of claim 19 further comprising:

a plurality of monitors;

an event schema vector storage location to store an event schema vector having a plurality of event occurrence indicator bits each associated with one of the plurality of monitors;

an event schema vector mask storage location to store an event schema vector mask having a plurality of event schema mask bits, each event schema mask bit being associated with one of the plurality of event occurrence indicator bits.

24. The apparatus of claim 19 wherein said program-definable condition comprises an occurrence of a program-defined combination of one or more microarchitectural events.

25. The apparatus of claim 24 further comprising a plurality of monitors to count microarchitectural events, wherein said program-defined combination of one or more microarchitectural events comprises each of said plurality of monitors reaching a programmable count.

26. An apparatus comprising:

multithreading execution logic capable of concurrent execution of multiple threads;

a plurality of monitors to monitor events within said multithreading execution logic;

thread switch logic coupled to said plurality of monitors, said thread switch logic to switch threads based at least partially on a programmable condition of one or more of said plurality of monitors.

27. The apparatus of claim 26 wherein said plurality of monitors are a plurality of performance monitors that monitor a plurality of microarchitectural conditions, wherein said plurality of performance monitors are also readable via an instruction.

28. The apparatus of claim 26 wherein said programmable condition comprises a number of greater than one cache misses.

29. The apparatus of claim 26 wherein said programmable condition is programmable at a user privilege level.

30. A method comprising:

programming a monitor to detect a processor condition;

spawning a helper thread in response to the processor condition occurring.

31. The method of claim 30 wherein programming the monitor comprises:

defining a microarchitectural condition.

32. The method of claim 31 wherein defining the microarchitectural condition comprises setting one or more programmable count values for one or more monitors.

33. The method of claim 30 wherein programming the monitor comprises writing to a model specific register.

34. A method comprising:

monitoring internal processing conditions for a programmable condition indicative of a plurality of internal hardware events while executing a first program portion;

transferring execution to a second program portion in response to the programmable condition occurring.

35. The method of claim 34 wherein said plurality of internal hardware events is an occurrence of a plurality of instances of a single type of event.

36. The method of claim 34 wherein said plurality of internal hardware events comprise one or more of each of a plurality of different microarchitectural events.

37. The method of claim 34 wherein said programmable condition comprises a plurality of monitors reaching user-definable metrics.

38. The method of claim 34 further comprising writing to a model specific register to set the programmable condition.

39. A method comprising:

setting a plurality of user-definable helper thread triggers to a first state;

simulating performance of a program a first time;

adjusting the plurality of user-definable helper thread triggers;

simulating performance of the program a second time;

selecting a preferred set of user-definable helper thread triggers based on performance of the program the first time and the second time;

40. The method of claim 39 further comprising:

including the preferred set of user-definable helper thread triggers in the program.

41. The method of claim 39 further comprising:

including a plurality of sets of user-definable helper thread triggers;

selecting one of the plurality of sets of user-definable helper thread triggers based on a processor identifier.

42. A system comprising:

a processor comprising a user programmable hardware monitor to detect a processor condition and to cause execution of a handler in response to the processor condition;

a storage medium to store the handler, the handler comprising at least one instruction that causes a helper thread to be generated.

43. The system of claim 42 wherein said processor condition comprises an indication of a plurality of processor events.

44. The system of claim 42 wherein said processor condition comprises the user programmable hardware monitor reaching a count of a single type of event.

45. The system of claim 42 wherein said processor condition comprises a plurality of user programmable hardware monitors reaching a plurality of counts for a plurality of processor-internal events.

46. The system of claim 45 further comprising a programmable enablement control to enable or disable execution of the handler in response to said plurality of user programmable hardware monitors reaching the plurality of counts.

47. The system of claim 42 further comprising a communications interface.

48. The system of claim 47 further comprising an update module to cause the system to receive via the communications interface a new processor condition to program into the programmable hardware monitor.

49. The system of claim 48 wherein said update module is also to cause the system to receive via the communications interface a new helper thread associated with said new processor condition.

50. A processor comprising:

execution resources to execute a plurality of instructions;

logic to cause a disruption of execution of said plurality of instructions in response to a programmable combination of a plurality of events of said execution resources, said plurality of events occurring after execution of a first instruction that enables detection of the programmable condition.

51. The processor of claim 50 wherein said disruption comprises a thread switch.

52. The processor of claim 50 wherein said disruption comprises calling a handler routine.

53. The processor of claim 50 wherein said instruction comprises a write to a register.

54. The processor of claim 50 wherein said instruction comprises an event-setting instruction.