Color filter configuration for a silicon wafer to be diced into photosensitive chips

• US 20040164229A1
• Filed: 02/23/2004
• Published: 08/26/2004
• Est. Priority Date: 03/08/2001
• Status: Abandoned Application

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Hosier, Paul A., Grimsley, Thomas, Jedlicka, Josef E.
• Application Number:
  US10/784,517
• Publication Number:
  US 20040164229A1
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

An architecture and manufacturing method for photosensitive chips, such as used in office equipment and digital cameras, involves creating grooves between chip areas in a wafer, and then placing a light-transmissive planar layer over the main surface of the wafer. The planar layer, which may be acrylic-based, creates a substantially planar surface over both the photosites in the chip areas and the grooves. The planar layer in turn supports one or more light-transmissive filtering layers. The arrangement avoids damage to the filtering layers when the wafer is diced along the grooves.

Claims

1. A method of making photosensitive chips for use in an imaging apparatus, comprising the steps of:

providing an integrated circuit wafer, the wafer comprising a first chip area defined in a main surface of the wafer, the first chip area including structure related to a first photosite, and a groove defined in the wafer, the groove defining at least one edge of the first chip area;

providing a light-transmissive planar layer over the main surface, the planar layer forming a planar surface substantially parallel with the main surface, the planar layer extending over the groove; and

dicing the wafer along the groove.

2. The method of claim 1, the planar layer comprising acrylic.

3. The method of claim 1, further comprising the step of providing a filtering layer disposed over the planar layer.

4. The method of claim 3, the filtering layer extending over the first photosite and over the groove.

5. The method of claim 3, the filtering layer comprising acrylic.

6. The method of claim 1, further comprising the step of providing in the chip area a ridge defined on the main surface between the photosite and the groove.

7. The method of claim 1, further comprising the step of providing in the chip area a ridge defined on the main surface between the photosite and the groove.