Structure and device including a tunneling piezoelectric switch and method of forming same

• US 20040164315A1
• Filed: 02/25/2003
• Published: 08/26/2004
• Est. Priority Date: 02/25/2003
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Demkov, Alexander A.
• Application Number:
  US10/372,281
• Publication Number:
  US 20040164315A1
• Time in Patent Office: Days
• US Class Current: 257/107
• CPC Class Codes: H01L 29/66939 with an active layer made of a group 13/15 material
• CPC Class Codes: H10N 39/00 Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

Abstract

Tunneling piezoelectric switch structures including high quality epitaxial layers of monocrystalline materials (26) grown overlying monocrystalline substrates (22) such as large silicon wafers are disclosed. The structures includes an accommodating buffer layer (24) spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer.

Claims

1. A piezoelectric switch structure comprising:

a monocrystalline substrate;

an accommodating buffer layer overlying the monocrystalline substrate;

a first piezoelectric portion formed overlying the accommodating buffer layer; and

.

a first semiconductor portion formed proximate the first piezoelectric portion, wherein the first piezoelectric portion and the first semiconductor portion are configured such that when a bias is applied across the first piezoelectric portion, the first piezoelectric portioned deforms and alters a tunneling rate between the first piezoelectric portion and the first semiconductor portion.

2. The piezoelectric switch structure of claim 1, further comprising an amorphous layer interposed between the monocrystalline substrate and the accommodating buffer layer.

3. The piezoelectric switch structure of claim 2, wherein the amorphous layer comprises silicon oxide.

4. The piezoelectric switch structure of claim 1, wherein the first piezoelectric portion comprises a material selected from ZnO and Pb(Zr,Ti)O₃.

5. The piezoelectric switch structure of claim 4, wherein the first piezoelectric portion comprises Pb_0.4Zr_0.6TiO₃.

6. The piezoelectric switch structure of claim 1, wherein first semiconductor portion is formed adjacent the first piezoelectric portion and formed overlying the accommodating buffer layer.

7. The piezoelectric switch structure of claim 1, wherein the first semiconductor portion comprises a material selected from the group consisting of silicon and gallium arsenide.

8. The piezoelectric switch structure of claim 1, wherein first semiconductor portion is formed overlying the first piezoelectric portion.

9. The piezoelectric switch structure of claim 8, further comprising a second piezoelectric portion formed overlying the first semiconductor portion and a second semiconductor portion overlying the second piezoelectric portion.

10. The piezoelectric switch structure of claim 9, wherein the second piezoelectric portion comprises a material selected from the group consisting of ZnO and Pb(Zr,Ti)O₃ and the second semiconductor portion comprises a material selected from the group consisting of silicon and gallium arsenide.

11. The piezoelectric switch structure of claim 1, further comprising an electronic device formed using the monocrystalline substrate.

12. A process for fabricating a piezoelectric switch structure comprising the steps of:

providing a monocrystalline substrate;

depositing a monocrystalline accommodating buffer film overlying the monocrystalline substrate;

epitaxially forming a first piezoelectric portion overlying the accommodating buffer film; and

forming a first monocrystalline semiconductor portion proximate the piezoelectric portion.

13. The process of claim 12, further comprising the step of forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the accommodating buffer film and the monocrystalline silicon substrate.

14. The process of claim 12, further comprising the step of exposing the monocrystalline accommodating buffer film to a temperature to convert at least a portion of the monocrystalline accommodating buffer film to an amorphous structure.

15. The process of claim 12, further comprising the steps of:

forming a second piezoelectric portion overlying the first semiconductor portion; and

forming a second semiconductor portion overlying the second piezoelectric portion.

16. The process of claim 12, wherein the step of epitaxially forming a first piezoelectric portion comprises applying Pb(Zr,Ti)O₃ using a spin-on, sol-gel technique.

17. The process of claim 16, further comprising the step of exposing the PB(Zr,Ti)O₃ material to calcine process.

18. A vertical piezoelectric switch structure comprising:

a monocrystalline silicon substrate;

an accommodating buffer layer comprising strontium titanate;

a first piezoelectric material portion formed overlying and in contact with the accommodating buffer layer; and

a first semiconductor material portion formed overlying the first piezoelectric material portion.

19. The vertical piezoelectric switch structure of claim 18, further comprising a first gate formed about a portion of the first piezoelectric material portion.

20. The vertical piezoelectric switch structure of claim 18, wherein the first piezoelectric material portion comprises Pb(Zr,Ti)O₃.

21. The vertical piezoelectric switch structure of claim 18, wherein the first semiconductor material portion comprises a material selected from the group consisting of silicon and gallium arsenide.

22. The vertical piezoelectric switch structure of claim 18, further comprising:

a second piezoelectric material portion formed overlying the first semiconductor material portion;

a second semiconductor material portion overlying the second piezoelectric material portion;

and a second gate formed about a portion of the second piezoelectric material portion.