Multilevel copper interconnects with low-k dielectrics and air gaps
First Claim
1. A multilevel wiring interconnect in an integrated circuit, comprising:
- a number of multilayer metal lines connecting to a number of silicon devices in a substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material.
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Accused Products
Abstract
Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance.
In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material. Structures and systems are similarly included in the present invention.
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Citations
17 Claims
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1. A multilevel wiring interconnect in an integrated circuit, comprising:
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a number of multilayer metal lines connecting to a number of silicon devices in a substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A multilevel wiring interconnect system, comprising:
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a number of multilayer metal lines connecting to a number of integrated circuit devices in a substrate; and
a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate, the low dielectric constant insulator having a number of air gaps therein. - View Dependent Claims (8, 9, 10, 11)
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12. A system having a multilevel wiring interconnect, comprising:
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an integrated circuit device; and
an integrated memory circuit operably coupled to the integrated circuit device, wherein the integrated memory circuit includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising;
a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material. - View Dependent Claims (13)
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14. A system, comprising:
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a processor; and
an integrated memory circuit coupled to the processor, wherein the integrated memory circuit further includes a multilevel wiring interconnect, the multilevel wiring interconnect comprising;
a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;
a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate; and
wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material. - View Dependent Claims (15, 16, 17)
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Specification