Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing

• US 20040164431A1
• Filed: 08/29/2003
• Published: 08/26/2004
• Est. Priority Date: 02/25/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Seaman, Kevin L., Wnek, Vernon M.
• Granted Patent: US 6,916,995 B2
• Time in Patent Office: Days
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/09227 : Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/0005 : for designing circuits by computer
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.

Claims

1. A ball grid array package comprising:

a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns, wherein at least one edge of said array is not fully populated with pads.

2. The package of claim 1, wherein said at least one edge includes a plurality of serially aligned conductive pads having a number of S spaces therebetween, wherein said number of S spaces is calculated according to

S=INT((E−

5)/3),

where;

E=a number of conductive pads in said at least one edge, if fully populated; and

INT is an INTEGER function, rounded down.

3. The package of claim 1, wherein said at least one edge includes a plurality of serially aligned conductive pads having a number of S spaces therebetween, wherein a ratio of said plurality of serially aligned conductive pads to said number of S spaces is at least two to one (2:

1).

4. The package of claim 1, wherein said at least one edge includes a plurality of serially aligned conductive pads having a space therebetween, wherein said space allows for at least one additional routing channel than when said at least one edge is fully populated.

5. The package of claim 4, wherein said space allows for two additional routing channels than when said at least one edge is fully populated.

6. The package of claim 1, wherein said at least one edge includes a plurality of serially aligned conductive pads having spaces therebetween created by missing pads, wherein said spaces create additional routing channels for signals from said conductive pads within said array to be routed external to said array through said at least one edge

7. The package of claim 6, wherein a higher proportion of said plurality of conductive pads are accessible by routing channels on a common layer with said conductive pads than when said at least one edge of said array is fully populated with pads.

8. The package of claim 6, wherein said array has a higher ratio of conductive pads that are externally routable on a single layer of said substrate material to conductive pads that are not externally routable on the single layer than when said at least one edge of said array is fully populated with pads.

9. A ball grid array land pattern comprising:

a plurality of conductive pads arranged in an array of rows and columns, wherein at least one edge of a perimeter of said array is not fully populated with conductive pads, whereby spaces created in said at least one edge by missing conductive pads create additional routing channels for signals from conductive pads within said array to be routed external to said array through said at least one edge.

10. The land pattern of claim 9, wherein a number S of said spaces is calculated according to

S=INT((E−

5)/3),

where;

E=a number of conductive pads in said at least one edge, if fully populated; and

INT is an INTEGER function, rounded down.

11. The land pattern of claim 9, wherein a ratio of conductive pads in said at least one edge to a number of said spaces in said at least one edge is at least two to one (2:

1).

12. A printed circuit board, comprising:

a substrate material; and

a plurality of conductive features on a first side of the printed circuit board, said conductive features including a plurality of conductive pads arranged in an array of rows and columns configured to receive mounting thereon of an integrated circuit device, wherein at least one edge of a perimeter of said array is not fully populated with conductive pads, whereby spaces created in said at least one edge by missing conductive pads create additional routing channels for signals from conductive pads within said array to be routed external to said array through said at least one edge.

13. The printed circuit board of claim 12, wherein a number S of said spaces is calculated according to

S=INT((E−

5)/3),

where;

E=a number of conductive pads in said at least one edge, if fully populated; and

INT is an INTEGER function, rounded down.

14. The printed circuit board of claim 12, wherein a ratio of conductive pads in said at least one edge to a number of said spaces in said at least one edge is at least two to one (2:

1).

15. A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising the steps of:

determining a number of required pads;

selecting a land pattern to yield the required pads;

determining a number of required perimeter routing channels; and

optimizing a size of the land pattern to yield the required perimeter routing channels, said optimizing step including under populating at least one perimeter edge of the land pattern.

16. The method of claim 15, wherein said optimizing step comprises:

adding at least one non-fully populated perimeter edge of pads of the land pattern.

17. The method of claim 16, wherein a first non-fully populated perimeter edge of pads of the at least one non-fully populated perimeter edge of pads includes a number S of spaces, wherein said adding step includes:

calculating the number S of spaces according to

S=INT((E−

5)/3),

where;

E=a number of pads in the first non-fully populated perimeter edge, if fully populated; and

INT is an INTEGER function, rounded down.

18. The method of claim 16, wherein a first non-fully populated perimeter edge of pads of the at least one non-fully populated perimeter edge of pads includes a number of spaces, wherein a ratio of pads in the first non-fully populated perimeter edge of pads to the number of spaces is at least two to one (2:

1).

19. The method of claim 15, wherein said optimizing step comprises:

removing pads from at least one existing fully populated perimeter edge of the land pattern.

20. The method of claim 19, wherein said removing step includes:

removing a number S of pads, wherein the number S of pads is calculated according to

S=INT((E−

5)/3),

where;

E=a number of pads in the at least one existing fully populated perimeter edge, when fully populated; and

INT is an INTEGER function, rounded down.

21. The method of claim 19, wherein a ratio of pads remaining in the at least one fully populated perimeter edge to the number of pads removed from the at least one fully populated perimeter edge is at least two to one (2:

1).

22. The method of claim 15, further comprising:

routing signals, from pads internal to the land pattern, through spaces formed by missing pads in the at least one non-fully populated perimeter edge.

23. The method of claim 22, wherein said routing step includes:

for each missing pad, routing three signals from pads internal to the land pattern through the space formed by the missing pad in the at least one non-fully populated perimeter edge.

24. The method of claim 15, wherein said optimizing step comprises:

if the selected land pattern provides excess pads, then removing pads from at least one existing perimeter edge until the required perimeter routing channels are made available; and

if the selected land pattern does not provide excess pads, then adding at least one non-fully populated perimeter edge of pads to the land pattern, wherein required perimeter routing channels are provided by openings formed by missing pads in the at least one non-fully populated perimeter edge.

25. A printed circuit board, comprising:

a first layer that comprises a substrate material;

a plurality of conductive features on a surface of the first layer, said conductive features including a first plurality of conductive pads arranged in a first array of rows and columns configured to receive mounting thereon of an integrated circuit device;

a second layer that comprises a substrate material;

a second plurality of conductive pads arranged in a second array of rows and columns on a surface of the second layer, wherein said second array includes fewer rows and columns than said first array; and

a plurality of conductive vias through the printed circuit board that electrically couple at least a portion of said first plurality of conductive pads to corresponding conductive pads of said second plurality of conductive pads,

wherein at least one edge of a perimeter of said first array is not fully populated with conductive pads, whereby spaces created in said at least one edge by missing conductive pads create additional routing channels for signals from conductive pads within said first array to be routed external to said first array through said at least one edge.

26. The printed circuit board of claim 25, wherein at least one edge of a perimeter of said second array is not fully populated with conductive pads, whereby spaces created in said at least one edge of said second array by missing conductive pads create additional routing channels for signals from conductive pads within said second array to be routed external to said second array through said at least one edge of said second array.

27. The printed circuit board of claim 25, wherein a number S of said spaces is calculated according to

S=INT((E−

5)/3),

where;

E=a number of conductive pads in said at least one edge, if fully populated; and

INT is an INTEGER function, rounded down.

28. The printed circuit board of claim 25, wherein a ratio of conductive pads in said at least one edge to a number of said spaces in said at least one edge is at least two to one (2:

1).

29. The printed circuit board of claim 26, wherein a number S of said spaces in said at least one edge of said second array is calculated according to

S=INT((E−

5)/3),

where;

E=a number of conductive pads in said at least one edge of said second array, if fully populated; and

INT is an INTEGER function, rounded down.

30. The printed circuit board of claim 26, wherein a ratio of conductive pads in said at least one edge of said second array to a number of said spaces in said at least one edge of said second array is at least two to one (2:

1).

31. A printed circuit board, comprising:

a plurality of layers that comprise a substrate material;

a plurality of conductive features on a surface of a first layer of the plurality of layers, said conductive features including a first plurality of conductive pads arranged in a first array of rows and columns configured to receive mounting thereon of an integrated circuit device;

a plurality of conductive pads arranged in an array of rows and columns on a surface of each subsequent layer of the plurality of layers, wherein said array on a subsequent layer of the plurality of layers includes fewer rows and columns than said array on a preceding layer; and

a plurality of conductive vias through the printed circuit board that electrically couple at least a portion of said first plurality of conductive pads to corresponding conductive pads of said plurality of conductive pads of each subsequent layer of the plurality of layers,

wherein at least one edge of a perimeter of said first array is not fully populated with conductive pads, whereby spaces created in said at least one edge by missing conductive pads create additional routing channels for signals from conductive pads within said first array to be routed external to said first array through said at least one edge.

32. The printed circuit board of claim 31, wherein at least one edge of a perimeter of an array of a subsequent layer of the plurality of layers is not fully populated with conductive pads, whereby spaces created in said at least one edge of said array of a subsequent layer of the plurality of layers by missing conductive pads create additional routing channels for signals from conductive pads within said array of a subsequent layer of the plurality of layers to be routed external to said array of a subsequent layer of the plurality of layers through said at least one edge.

33. A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising:

(1) determining a number of required pads;

(2) determining a number of layers of the printed circuit board to have routing channels;

(3) selecting a land pattern to yield the required pads;

(4) determining a number of required perimeter routing channels for an array of conductive pads on each layer of the determined number of layers; and

(5) optimizing a size of the land pattern to yield the required perimeter routing channels in each layer, said optimizing step including under populating at least one perimeter edge on at least one layer.

34. The method of claim 33, wherein step (5) comprises:

adding at least one non-fully populated perimeter edge of pads on the at least one layer.

35. The method of claim 34, wherein a first non-fully populated perimeter edge of pads of the at least one non-fully populated perimeter edge of pads includes a number S of spaces, wherein said adding step includes:

calculating the number S of spaces according to

S=INT((E−

5)/3),

where;

E=a number of pads in the first non-fully populated perimeter edge, if fully populated; and

INT is an INTEGER function, rounded down.

36. The method of claim 34, wherein a first non-fully populated perimeter edge of pads of the at least one non-fully populated perimeter edge of pads includes a number of spaces, wherein said adding step comprises:

adding spaces to the first non-fully populated perimeter edge of pads such that a ratio of pads in the first non-fully populated perimeter edge of pads to the number of spaces is at least two to one (2;

1).

37. The method of claim 33, wherein step (5) comprises:

removing pads from at least one existing fully populated perimeter edge on the at least one layer.

38. The method of claim 37, wherein said removing step includes:

removing a number S of pads, wherein the number S of pads is calculated according to

S=INT((E−

5)/3),

where;

E=a number of pads in the at least one existing fully populated perimeter edge, when fully populated; and

INT is an INTEGER function, rounded down.

39. The method of claim 37, wherein said removing step comprises:

removing pads such that a ratio of pads remaining in the at least one fully populated perimeter edge to the number of pads removed from the at least one fully populated perimeter edge is at least two to one (2;

1).

40. The method of claim 33, further comprising:

routing signals, from pads internal to the array of pads on the at least one layer, through spaces formed by missing pads in the at least one non-fully populated perimeter edge.

41. The method of claim 40, wherein said routing step includes:

for each missing pad, routing three signals from pads internal to the array of pads on the at least one layer through the space formed by the missing pad in the at least one non-fully populated perimeter edge.

42. The method of claim 33, wherein step (5) comprises:

if the selected land pattern provides excess pads, then removing pads from at least one existing perimeter edge until the required perimeter routing channels are made available; and

if the selected land pattern does not provide excess pads, then adding at least one non-fully populated perimeter edge of pads to the land pattern, wherein required perimeter routing channels are provided by openings formed by missing pads in the at least one non-fully populated perimeter edge.