Circuit for programmable stepless clock shifting

• US 20040164779A1
• Filed: 11/25/2003
• Published: 08/26/2004
• Est. Priority Date: 02/21/2003
• Status: Active Grant

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Novellini, Paolo, Cucchi, Silvio
• Granted Patent: US 6,995,593 B2
• Time in Patent Office: Days
• US Class Current: 327/231
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

Abstract

The present invention provides for a circuit for programmable stepless clock shifting, consisting of a splitter generating a 0° and a 90° shifted clocks from a reference clock, and an interpolator of the two shifted clocks, which provides at the output the desired pre-set clock phase.

Claims

1. Circuit for programmable stepless clock shifting comprising:

a splitter, receiving a clock reference and generating two 90′

-shifted clock phases;

an interpolator receiving said two 90′

-shifted clock phases and two coefficients, and supplying a programmable phase clock, which has a phase shift with respect to said clock reference that depends only on said two coefficients.

2. Circuit according to claim 1, wherein said splitter comprises:

a delay circuit receiving said clock reference and supplying a delayed clock;

an adder and a subtractor of said clock reference and said delayed clock, supplying at the output said two 90′

-shifted clock phases.

3. Circuit according to claim 2, wherein said splitter further comprises at the output two squarers of said two 90′

-shifted clock phases, so as the latter have the same amplitude.

4. Circuit according to claim 2, wherein the delay introduced by said delay circuit is typically Δ

=90°

±

50%, and is

Δ

≠

π

+kπ

, k={0, ±

1, ±

2, . . . }

5. Circuit according to claim 1, wherein said interpolator comprises:

a first and second multiplier, respectively receiving one of said two 90°

-shifted clock phases and a first and second coefficient;

an adder receiving the outputs of said first and second multiplier and supplying said programmable phase clock.

6. Circuit according to claim 5, wherein said first and second coefficient have a value of respectively sin Φ

and cos Φ

, such that the following relationship is performed;

sin(ω

t+Φ

)=sin(ω

t)cos Φ

+cos(ω

t)sin Φ

where Φ

is said programmable phase of the programmable phase clock;

sin(ω

t+Φ

) is the frequency of said programmable phase clock;

sin(ω

t) and cos(ω

t) are the frequencies of said two 90′

-shifted clock phases.

7. Circuit according to claim 5, wherein said first and second coefficient are selected from a memory table, addressed according to the wanted programmable phase.

8. Circuit according to claim 6, wherein said first and second coefficient are selected from a memory table, addressed according to the wanted programmable phase.