Low power, area-efficient circuit to provide clock synchronization
First Claim
1. A method for controllably asserting a clock signal on a clock signal bus of an integrated circuit comprising the steps of:
- in the absence of a first clock signal being coupled to a prescribed conductor of said integrated circuit, coupling a second clock signal as a default clock signal to said clock signal bus of said integrated circuit; and
in response to said first clock signal being coupled to said prescribed conductor of said integrated circuit, interrupting the coupling of said second clock signal to said clock signal bus of said integrated circuit and, in place thereof, coupling said first clock signal to said clock signal bus of said integrated circuit.
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Accused Products
Abstract
A clock signal generator, which requires no clock selection pin includes a multiplexer to which external and internal clocks are applied. The external clock is further coupled directly and via an inverting delay to a logic circuit, the output of which controls a switching device connected across a capacitor. The capacitor is coupled to a current source and to a comparator that is coupled to a reference voltage. The comparator output serves as the select control for the multiplexer. The switching device repeatedly discharges the capacitor in response to the external clock signal, but otherwise allows the capacitor to be charged by the current source. The external clock signal is coupled to the output of the multiplexer, as long as the capacitor is repeatedly discharged by the external clock signal at a frequency sufficient to maintain the voltage across the capacitor less than the reference voltage.
12 Citations
15 Claims
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1. A method for controllably asserting a clock signal on a clock signal bus of an integrated circuit comprising the steps of:
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in the absence of a first clock signal being coupled to a prescribed conductor of said integrated circuit, coupling a second clock signal as a default clock signal to said clock signal bus of said integrated circuit; and
in response to said first clock signal being coupled to said prescribed conductor of said integrated circuit, interrupting the coupling of said second clock signal to said clock signal bus of said integrated circuit and, in place thereof, coupling said first clock signal to said clock signal bus of said integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A circuit for controllably asserting either an internal clock signal or an external clock signal on a clock signal bus of an integrated circuit comprising:
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an internal clock signal transport path that is operative, in the absence of said external clock signal being coupled to a prescribed conductor of said integrated circuit, to couple said internal clock signal as a default clock signal to said clock signal bus of said integrated circuit; and
an external clock signal transport path that is operative, in response to said external clock signal being coupled to said prescribed conductor of said integrated circuit, to interrupt the coupling of said internal clock signal to said clock signal bus of said integrated circuit in and, in place thereof, to couple said external clock signal to said clock signal bus of said integrated circuit. - View Dependent Claims (8, 9, 10, 11, 12)
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- 13. A clock signal generator that is exclusive of a clock selection pin comprising a multiplexer having a first input to which an external clock signal is applied and a second input to which an internal clock signal is applied, said external clock signal being further coupled to an inverting delay and to a first input of a logic circuit, the output of said inverting delay being coupled to a second input of said logic circuit, said logic circuit having an output thereof coupled to a control input of a switching device, said switching device having a current flow path coupled to a current source and in parallel with a capacitor, and wherein a common connection between said current source and said electrical energy storage device is coupled to a first input of a comparator, said comparator having a second input coupled to receive a reference voltage, and an output coupled to a select port of said multiplexer, and wherein said switching device is operative to repeatedly discharge the capacitor in accordance with said external clock signal, but to otherwise allow the capacitor to be charged by the current source, so that said external clock signal is coupled to the output of said multiplexer, as long as the capacitor is repeatedly discharged by said external clock signal at a frequency sufficient to maintain the voltage across said capacitor less than a prescribed reference voltage.
Specification