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Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation

  • US 20040165421A1
  • Filed: 02/24/2004
  • Published: 08/26/2004
  • Est. Priority Date: 08/08/2002
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a plurality of planar memory arrays, each planar memory array comprising a plurality of resistive memory cells arranged in rows and columns, the memory cells of a column being commonly coupled to a sense line, each sense line of an array being commonly electrically coupled to an associated sense line of each of said other memory arrays, each of said memory cells having an associated read line; and

    an access transistor for electrically connecting said commonly electrically coupled sense lines to a sense amplifier during a read operation.

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