Trench MIS device with thick oxide layer in bottom of gate contact trench

• US 20040166636A1
• Filed: 11/25/2003
• Published: 08/26/2004
• Est. Priority Date: 07/03/2001
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Granted Patent: US 7,009,247 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.

Claims

5-1. The method of claim 1 wherein said trench is located in a gate bus region of said device.

10. A trench MIS device formed in a semiconductor substrate and comprising and active region and an inactive region, said active region comprising:

a first trench containing a first conductive gate material;

a source region in said substrate; and

a body region adjacent a side wall of said trench, said trench being lined with a thin insulating layer adjacent said body region;

said inactive region comprising;

a second trench containing a second conductive material, said second conductive material being in electrical contact with said first conductive material;

a relatively thin insulating layer on a side wall of said second trench;

a relatively thick insulating layer on a bottom of said second trench; and

a gate bus in contact with said second conductive material.

11. The trench MIS device of claim 10 wherein said relatively thin insulating layer covers a corner region between said bottom and said side wall of said second trench.

12. The trench MIS device of claim 10 comprising a transition region between said relatively thick insulating layer and said relatively thin insulating layer, said transition region comprising a graduated insulating layer abutting said relatively thick and relatively thin insulating layers, a thickness of said graduated insulating layer decreasing gradually in the direction from said relatively thick insulating layer towards said relatively thin insulating layer.