METHOD OF FABRICATING SEMICONDUCTOR DEVICE

• US 20040166656A1
• Filed: 02/25/2004
• Published: 08/26/2004
• Est. Priority Date: 08/28/1997
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Oishi, Kentaro, Kudo, Satoshi, Nakazawa, Yoshito, Shigematsu, Takashi, Uesawa, Kozo, Kobayashi, Masayoshi, Imai, Yasuo, Ohnishi, Akihiro, Numazawa, Sumito, Kubo, Sakae
• Granted Patent: US 6,803,281 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A method of fabricating a semiconductor device comprising the steps of:

(a) forming a trench in a semiconductor substrate having a first semiconductor region of a first conductivity type, from a major surface of the semiconductor substrate in a depth direction thereof;

(b) forming a gate insulating film including a thermal oxide film and a deposition film over the internal surface of the trench;

(c) forming a gate electrode over the gate insulating film in the trench; and

(d) introducing, after said step (c), impurities into the semiconductor substrate to form a second semiconductor region of a second conductivity type; and

(e) introducing, after said step (c), impurities into the semiconductor substrate to form a third semiconductor region of the first conductivity type,

the third semiconductor region being formed at a place deeper than the first semiconductor region,

the second semiconductor region being formed between the third semiconductor region and the first semiconductor region in the depth direction.

2. A method of fabricating a semiconductor device according to claim 1, wherein the thermal oxide film is formed by thermal oxidation in an oxygen gas atmosphere or a water vapor atmosphere, and the deposition film is formed by a chemical vapor deposition method.

3. A method of fabricating a semiconductor device according to claim 1, further comprising the step of:

etching the top edge portion and the bottom edge portion of the trench between said step (a) and said step (b) to form the top edge portion and the bottom edge portion into gently-sloping shapes, respectively.

4. A method of fabricating a semiconductor device according to claim 1, further comprising the step of:

forming a sacrifice thermal oxide film over the internal surface of the trench; and

removing the sacrifice thermal oxide film,

said step being conducted between said step (a) and said step (b).

5. A method of fabricating a semiconductor device according to claim 4, wherein the sacrifice thermal oxide film is formed in an oxygen gas atmosphere of 1,000°

C. or higher or in an oxygen gas atmosphere diluted with a nitrogen gas.

6. A method of fabricating a semiconductor device according to claim 1, wherein the deposition film is formed by a chemical vapor deposition method, the deposition film being a silicon oxide film, a silicon nitride film or an acid nitride film.

7. A method of fabricating a semiconductor device according to claim 2, wherein the first semiconductor region serves as a drain region of a MISFET, the second semiconductor region serves as a channel region of the MISFET, and the third semiconductor region serves as a source region of the MISFET.

8. A method of fabricating a semiconductor device according to claim 2, wherein the trench is formed by etching a silicon nitride film formed on the major surface of the semiconductor substrate and the semiconductor substrate, and the silicon nitride film is removed after said step (c).

9. A method of fabricating a semiconductor device comprising the steps of:

(a) etching a semiconductor substrate having a first semiconductor region of a first conductivity type which serves as a drain region, and a silicon nitride film formed over a major surface of the semiconductor substrate, to form a trench from the major surface of the semiconductor substrate in a depth direction thereof;

(b) forming a gate insulating film including a thermal oxide film and a deposition film over the internal surface of the trench;

(c) forming a gate electrode over the gate insulating film in the trench;

(d) introducing, after said step (c), impurities into the semiconductor substrate to form a second semiconductor region of a second conductivity type which serves as a channel region; and

(e) introducing, after said step (c), impurities into the semiconductor substrate to form a third semiconductor region of the first conductivity type which serves as a source region,

the third semiconductor region being formed at a place deeper than the first semiconductor region,

the second semiconductor region being formed between the third semiconductor region and the first semiconductor region in the depth direction, and

the silicon nitride film being removed at least after said step (b).

10. A method of fabricating a semiconductor device according to claim 9, further comprising the step of:

etching the top edge portion and the bottom edge portion of the trench to form the top edge portion and the bottom edge portion into gently-sloping shapes, respectively,

said step being conducted between said step (a) and said step (b).

11. A method of fabricating a semiconductor device according to claim 9, further comprising the step of:

forming a sacrifice thermal oxide film over the internal surface of the trench; and

removing the sacrifice thermal oxide film,

said step being conducted between said step (a) and said step (b).

12. A method of fabricating a semiconductor device according to claim 11, wherein the sacrifice thermal oxide film is formed in an oxygen gas atmosphere of 1,000°

C. or higher or in an oxygen gas atmosphere diluted with a nitrogen gas.

13. A method of fabricating a semiconductor device according to claim 9, wherein the thermal oxide film is formed by thermal oxidation in an oxygen gas atmosphere or in a water vapor atmosphere, and the deposition film is formed by a chemical vapor deposition method.

14. A method of fabricating a semiconductor device according to claim 9, wherein the silicon nitride film is removed after said step (c).

15. A method of forming a MISFET comprising the steps of:

(a) etching a silicon nitride film formed over a major surface of a semiconductor substrate, and the semiconductor substrate, to form a trench from the major surface of the semiconductor substrate in a depth direction thereof;

(b) forming a gate insulating film of the MISFET including a thermal oxide film and a deposition film over the internal surface of the trench; and

(c) forming a gate electrode of the MISFET over the gate insulating film in the trench;

the silicon nitride film being removed at least after said step (b).

16. A method of forming a MISFET according to claim 15, wherein the first semiconductor region in said step (a) has a first semiconductor region of a first conductivity type which serves as a drain region,

after said step (c), impurities are introduced into the semiconductor substrate to form a second semiconductor region of a second conductivity type which serves as a channel region,

after said step (c), impurities are introduced into the semiconductor substrate to form a third semiconductor region of the first conductivity type which serves as a source region,

the third semiconductor region is formed at a place deeper than the first semiconductor region, and

the second semiconductor region is formed between the third semiconductor region and the first semiconductor region in the depth direction.

17. A method of forming a MISFET according to claim 15, further comprising the step of:

etching the top edge portion and the bottom edge portion of the trench between said step (a) and said step (b) to form the top edge portion and the bottom edge portion into gently-sloping shapes, respectively.

18. A method of forming a MISFET according to claim 15, further comprising the step of:

forming a sacrifice thermal oxide film over the internal surface of the trench; and

removing the sacrifice thermal oxide film,

said step being conducted between said step (a) and said step (b).

19. A method of fabricating a MISFET according to claim 18, wherein the sacrifice thermal oxide film is formed in an oxygen gas atmosphere of 1,000°

C. or higher or in an oxygen gas atmosphere diluted with a nitrogen gas.

20. A method of fabricating a MISFET according to claim 15, wherein the thermal oxide film is formed by thermal oxidation in an oxygen gas atmosphere or in a water vapor atmosphere, and the deposition film is formed by a chemical vapor deposition method.

21. A method of fabricating a semiconductor device according to claim 15, wherein the silicon nitride film is removed after said step (c).