Method and apparatus for performing DC offset cancellation in a receiver

• US 20040166824A1
• Filed: 02/24/2004
• Published: 08/26/2004
• Est. Priority Date: 11/14/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Franca-Neto, Luiz M.
• Granted Patent: US 7,233,780 B2
• Time in Patent Office: Days
• US Class Current: 455/296
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/45982 by using a feedforward circuit
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

An amplification system for reducing DC offset in an input signal uses a low pass filter to isolate a DC component of the input signal. The system then subtracts the DC component from the input signal. In one embodiment, the system includes first and second amplifiers in addition to the low pass filter. The first amplifier amplifies the input signal to generate a first amplified signal at a differential output port of the amplification system. The second amplifier amplifies a low pass filtered version of the input signal to generate a second amplified signal at the differential output port of the amplification system. The outputs of the first and second amplifiers are connected to the differential output port of the amplification system in such a way that the first and second signals combine 180 degrees out of phase at the output port. An automatic gain control circuit is also provided that automatically adjusts the gain of the amplification system without changing a bias level associated with the first and second amplifiers.

Claims

1. A method for suppressing DC offset within a baseband signal in a receiver, comprising:

receiving a baseband signal having a DC offset;

generating a first amplified signal using said baseband signal;

generating a second amplified signal using said baseband signal, said second amplified signal having reduced high frequency content compared to said first amplified signal; and

subtracting said second amplified signal from said first amplified signal to generate an output baseband signal having reduced DC offset.

2. The method claimed in claim 1, wherein:

generating a second amplified signal includes using a low pass filter.

3. The method claimed in claim 1, wherein:

generating first and second amplified signals includes using first and second amplifiers, respectively, said first and second amplifiers having substantially the same gain.

4. The method claimed in claim 1, wherein:

generating a second amplified signal includes low pass filtering said baseband signal to generate a filtered signal and then amplifying said filtered-signal.

5. The method claimed in claim 1, wherein:

said first and second amplified signals are each differential signals, wherein subtracting said second amplified signal from said first amplified signal includes applying said first and second amplified signals to a pair of differential output terminals approximately 180 degrees out of phase.

6. An amplification system to reduce DC offset in a signal, comprising:

first and second differential input terminals;

first and second differential output terminals;

a first amplifier, coupled to said first and second differential input terminals and said first and second differential output terminals, to amplify a signal received at said first and second differential input terminals to generate a first amplified signal at said first and second differential output terminals;

a low pass filter (LPF) coupled to said first and second differential input terminals, said LPF to filter said signal received at said first and second differential input terminals to generate a filtered signal at an output port of said LPF, said filtered signal having reduced high frequency content; and

a second amplifier coupled to said output port of said LPF and to said first and second differential output terminals to amplify said filtered signal to generate a second amplified signal at said first and second differential output terminals, said second amplifier being connected to said first and second differential output terminals in a manner that causes said first and second amplified signals to subtract at said first and second differential output terminals.

7. The amplification system claimed in claim 6, wherein:

said LPF blocks frequencies outside a small band about DC.

8. The amplification system claimed in claim 6, wherein:

said LPF includes first and second shunt capacitors, said first shunt capacitor being connected between a first node on a first differential line of said LPF and a ground node and said second shunt capacitor being connected between a second node on a second differential line of said LPF and said ground node.

9. The amplification system claimed in claim 8, wherein:

said LPF includes first and second series resistors, said first series resistor being connected between an input node on said first differential line of said LPF and said first node and said second series resistor being connected between an input node on said second differential line of said LPF and said second node.

10. The amplification system claimed in claim 6, wherein:

said first and second amplifiers are matched to one another.

11. The amplification system claimed in claim 6, wherein:

said first and second amplifiers have substantially the same gain.

12. The amplification system claimed in claim 6, wherein:

said first and second amplifiers each include first and second differential output lines, said first and second differential output lines of said second amplifier being cross coupled to said first and second differential output lines of said first amplifier.

13. The amplification system claimed in claim 6, further comprising:

an automatic gain control (AGC) circuit connected between said first and second differential output terminals of said amplification system to automatically adjust a gain of said amplification system without changing a bias level of said first and second amplifiers.

14. The amplification system claimed in claim 13, wherein:

said AGC circuit includes a variable impedance device connected between said first and second differential output terminals to change an impedance between said first and second differential output terminals based on a signal level on at least one of said first and second differential output terminals.

15. The amplification system claimed in claim 6, wherein:

said first and second amplifiers and said low pass filter are comprised of CMOS structures.

16. A receiver comprising:

a mixer having an RF port, an LO port, and a baseband port, said RF port to receive a communication signal and said LO port to receive a local oscillator signal, said mixer to output a baseband signal at said baseband port that includes information derived from said communication signal, said baseband signal including a DC offset component; and

a baseband amplification subsystem comprising;

first and second differential input terminals coupled to said baseband

port of said mixer to receive said baseband signal;

first and second differential output terminals;

a first amplifier, coupled to said first and second differential input terminals and said first and second differential output terminals, to amplify said baseband signal to generate a first amplified signal at said first and second differential output terminals;

a low pass filter (LPF) coupled to said first and second differential input terminals to filter said baseband signal to generate a filtered signal at an output port of said LPF, said filtered signal having reduced high frequency content; and

a second amplifier, coupled to said output port of said LPF and to said first and second differential output terminals, to amplify said filtered signal to generate a second amplified signal at said first and second differential output terminals, said second amplifier being connected to said first and second differential output terminals in a manner that causes said first and second amplified signals to subtract at said first and second differential output terminals;

said baseband amplification subsystem generating an amplified baseband signal having a suppressed DC offset component at said first and second differential output terminals.

17. The receiver claimed in claim 16, further comprising:

an automatic gain control (AGC) circuit connected between said first and second differential output terminals of said baseband amplification subsystem to automatically adjust a gain of said baseband amplification subsystem without changing a bias level associated with said baseband amplification subsystem.

18. The receiver claimed in claim 17, wherein:

said AGC circuit includes a variable impedance device connected between said first and second differential output terminals of said baseband amplification subsystem to change an impedance between said first and second differential output terminals based on a signal level on at least one of said first and second differential output terminals.

19. The receiver claimed in claim 17, further comprising a second baseband amplification subsystem including:

third and fourth differential input terminals coupled to said first and second differential output terminals to receive said amplified baseband signal;

third and fourth differential output terminals;

a third amplifier, coupled to said third and fourth differential input terminals and said third and fourth differential output terminals, to amplify said amplified baseband signal to generate a third amplified signal at said third and fourth differential output terminals;

a second LPF coupled to said third and fourth differential input terminals to filter said amplified baseband signal to generate a second filtered signal at an output port of said second LPF; and

a fourth amplifier, coupled to said output port of said second LPF and to said third and fourth differential output terminals, to amplify said second filtered signal to generate a fourth amplified signal at said third and fourth differential output terminals, said fourth amplifier being connected to said third and fourth differential output terminals in a manner that causes said third and fourth amplified signals to subtract at said third and fourth differential output terminals.

20. The receiver claimed in claim 19, wherein:

said AGC circuit adjusts the gain of said baseband amplification subsystem so that said amplified baseband signal does not overdrive said third amplifier.

21. The receiver claimed in claim 20, wherein:

a DC bias signal on said first and second differential output terminals provides an input bias signal for said second baseband amplification subsystem, wherein said AGC circuit does not affect said DC bias signal as it adjusts said gain.