Input pipeline registers for a node in an adaptive computing engine

• US 20040168044A1
• Filed: 07/23/2003
• Published: 08/26/2004
• Est. Priority Date: 10/28/2002
• Status: Active Grant

• Current Assignee: QST Holdings LLC
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Ramchandran, Amit
• Granted Patent: US 7,249,242 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Input pipeline registers are provided at inputs to functional units and data paths in a adaptive computing machine. Input pipeline registers are used to hold last-accessed values and to immediately place commonly needed constant values, such as a zero or one, onto inputs and data lines. This approach can reduce the time to obtain data values and conserve power by avoiding slower and more complex memory or storage accesses. Another embodiment of the invention allows data values to be obtained earlier during pipelined execution of instructions. For example, in a three stage fetch-decode-execute type of reduced instruction set computer (RISC), a data value can be ready from a prior instruction at the decode or execute stage of a subsequent instruction.

Claims

1. A computational unit in an adaptable computing engine, wherein the computational unit includes a clock signal for determining a processor cycle, the computational unit comprising

one or more functional units coupled by a bus, wherein the one or more functional units include functional unit inputs;

at least one register coupled between the bus and at the input of least one functional unit input; and

a control signal for selectively causing the at least one register to hold a data value from the bus for one or more processor cycles.

2. The computational unit of claim 1, wherein the register includes

circuitry for selectively providing a constant value.

3. The computational unit of claim 1, further comprising

a coupling of a pair of registers such that the pair of registers is responsive to a control signal value.

4. The computational unit of claim 3, further comprising

control circuitry for setting the pair of registers into predetermined states based on the control signal value.

5. The computational unit of claim 4, wherein the pair of registers includes first and second registers, wherein the predetermined states include one or more of the following for the first and second registers, respectively:

load, hold;

load, clear;

hold, load;

clear, load;

hold, hold;

hold, clear;

clear, hold; and

clear, clear.

6. The computational unit of claim 4, wherein the control signal value comprises 7 bits.

9. The method of claim 1, further comprising

coupling a pair of registers such that the pair of registers is responsive to a control signal value.

10. The method of claim 9, further comprising

providing control circuitry for setting the pair of registers into predetermined states based on the control signal value.

11. The computational unit of claim 9, wherein the pair of registers includes first and second registers and wherein the predetermined states include one or more of the following for the first and second registers, respectively:

load, hold;

load, clear;

hold, load;

clear, load;

hold, hold;

hold, clear;

clear, hold; and

clear, clear.

12. The computational unit of claim 9, wherein the control signal value comprises 7 bits.

7. A method for providing data in a computational unit in an adaptable computing engine, the method comprising

including registers at inputs to functional units, wherein the registers are coupled to a bus for obtaining data from the bus;

including a control signal for selectively causing the registers to hold a data value from the bus for one or more processor cycles.

8. The method of claim 7, wherein the register includes

circuitry for selectively providing a constant value.

13. An apparatus for providing a data value in a computational unit in an adaptable computing engine, wherein the computational unit includes a multi-stage execution pipeline, the apparatus comprising

one or more functional units coupled by a bus, wherein the one or more functional units include functional unit inputs;

at least one input register coupled between the bus and at least one functional unit input; and

a data path from an input register to a given stage in the execution pipeline so that a value provided by the register is available for use at a time of execution of the given stage.

14. The apparatus of claim 13, wherein the register includes

circuitry for selectively providing a constant value.

16. The apparatus of claim 13, wherein the register includes circuitry for selectively providing a constant value.

15. A method for providing a data value in a computational unit in an adaptable computing engine, wherein the computational unit includes a multi-stage pipeline, the method comprising

coupling one or more functional units to a bus, wherein the one or more functional units include functional unit inputs;

coupling at least one register between the bus and at least one functional unit input; and

providing a data path from a register to a given stage in the execution pipeline so that a value provided by the register is available for use at a time of execution of the given stage.