Redundant memory system and memory controller used therefor

• US 20040168101A1
• Filed: 04/09/2003
• Published: 08/26/2004
• Est. Priority Date: 04/09/2002
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kubo, Atsushi
• Application Number:
  US10/409,580
• Publication Number:
  US 20040168101A1
• Time in Patent Office: Days
• US Class Current: 714/6
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD

Abstract

A redundant memory system makes it possible to replace a failed one of memory modules incorporated with a new memory sub-module during the energized or in-service state even if the OS used in a system does not support the memory redundancy function. This memory system includes memory modules inserted into respective slots, and a memory controller connected to the slots and providing redundancy. The controller defines one of the modules as a parity memory and its remainder as data memories. A first parity code is generated from desired data to be stored and written into the parity memory while the desired data are written into the respective data memories. The desired data are read from the respective data memories and the first parity code is read from the parity memory to thereby conduct a parity check operation and an error correction operation of the desired data using the desired data and the first parity code, resulting in the redundancy.

Claims

1. A redundant memory system comprising:

memory slots;

memory modules for storing data, the modules being inserted into the respective slots; and

a memory controller connected to the slots and providing redundancy;

wherein the controller defines one of the modules as a parity memory and its remainder as data memories;

and wherein a first parity code is generated from desired data to be stored and written into the parity memory and the desired data are written into the respective data memories;

and wherein the desired data are read from the respective data memories and the first parity code is read from the parity memory to thereby conduct a parity check operation and an error correction operation of the desired data using the desired data and the first parity code, resulting in the redundancy.

2. The memory system according to claim 1, wherein the memory slots are capable of hot plugging or hot swapping operation, wherein a failed one of the memory modules is replaceable with a new memory module in an energized state of the memory system.

3. The memory system according to claim 1, wherein the controller generates a second parity code using the desired data read from respective data memories and then, compares the second parity code with the first parity code read from the parity memory;

and wherein the parity check operation is conducted by comparing the second parity code with the first parity code;

and wherein when one of the modules defined as the data memories is failed, the error correction operation of the desired data is conducted by reconfiguring the desired data read from the remaining non-failed data memories and the first parity data read from the parity memory.

4. A redundant memory system comprising:

n memory slots, where n is an integer greater than one;

n memory modules for storing data, the modules being inserted into the respective slots; and

a memory controller connected to the slots and providing redundancy;

wherein the controller comprises

n ECC/ChIPKILL circuits connected to the respective slots, for ECC code generation, error check, data reconfiguration, and ChipKill operation;

a parity-generation/check/reconfiguration circuit connected to the n ECC/CHIPKILL circuits, the parity-generation/check/reconfiguration circuit defining one of the n modules as a parity memory and its remainder as (n−

1) data memories;

wherein a first parity code is generated from desired data to be stored and written into the parity memory while the desired data are written into the respective (n−

1) data memories; and

wherein a second parity code is generated from the desired data read from the (n−

1) data memories and compared with the first parity code read from the parity memory, thereby conducting an error checking operation; and

wherein when one of the (n−

1) data memories is failed, the desired data is reconfigured using the first parity code and the (n−

2) data memories other than the failed one; and

an error count circuit including a generation counter register for storing generation counts of FCC errors and ChipKill errors, and a comparator for comparing the generation counts with a threshold;

wherein the comparator outputs an interrupt signal to the upper system when one of the generation counts exceeds the threshold.

5. The memory system according to claim 4, wherein the parity-generation/check/reconfiguration circuit has the function deblocking the desired data to (n−

1) parts of data;

of;

generating the first parity code through an Exclusive OR operation of the (n−

1) parts of data;

writing the (n−

1) parts of data into the respective (n−

1) data memories;

reading the (n−

1) parts of data from the respective (n−

1) data memories;

generating the second parity code through an Exclusive OR operation of the (n−

1) parts of data read from the respective (n −

1) data memories; and

comparing the second parity code with the first parity code to generate a result for error finding;

wherein when no error is found according to the result, the (n−

1) parts of data read are blocked to reconstitute the desired data and output the said desired data;

and wherein when an error is found in one of the (n−

1) parts of data read according to the result, the error is corrected using the first parity data and the remaining (n−

2) parts of data other than the failed one, and the (n−

1) parts of data read are blocked to reconstitute the desired data.

6. A memory controller comprising:

means for defining one of memory modules inserted into respective memory slots as a parity memory and its remainder as data memories;

means for generating a first parity code from desired data to be stored;

means for writing the desired data into the respective data memories and the first parity code into the parity memory; and

means for reading the desired data from the respective data memories and the first parity code from the parity memory to thereby conduct a parity check operation and an error correction operation of the desired data using the desired data and the first parity code, resulting in the redundancy.

7. The memory controller according to claim 6, wherein the memory slots are capable of hot plugging or hot swapping operation, wherein a failed one of the memory modules is replaceable with a new memory module in an energized state of the memory system.

8. The memory controller according to claim 6, wherein a second parity code is generated using the desired data read from respective data memories and then, the second parity code is compared with the first parity code read from the parity memory;

and wherein the parity check operation is conducted by comparing the second parity code with the first parity code;

and wherein when one of the modules defined as the data memories is failed, the error correction operation or the desired data is conducted by reconfiguring the desired data read from the remaining non-failed data memories and the first parity data read from the parity memory.

9. A memory controller comprising:

n ECC/ChIPRILL circuits connected to respective n memory slots, for ECC code generation, error check, data reconfiguration, and ChipKill operation, where n is an integer greater than one;

a parity-generation/check/reconfiguration circuit connected to the n ECC/CHIPKILL circuits, the parity-generation/check/reconfiguration circuit defining one of n memory modules as a parity memory and its remainder as (n−

1) data memories;

wherein a first parity code is generated from desired data to be stored and written into the parity memory while the desired data are written into the respective (n−

1) data memories; and

wherein a second parity code is generated from the desired data read from the (n−

1) data memories and compared with the first parity code read from the parity memory, thereby conducting an error checking operation; and

wherein when one of the (n−

1) data memories is failed, the desired data is reconfigured using the first parity code and the (n−

2) data memories other than the failed one; and

an error count circuit including a generation counter register for storing generation counts of ECC errors and ChipKill errors, and a comparator for comparing the generation counts with a threshold;

wherein the comparator outputs an interrupt signal to the upper system when one of the generation counts exceeds the threshold.

10. The memory controller according to claim 9, wherein the parity-generation/check/reconfiguration circuit has the function of:

deblocking the desired data to (n−

1) parts of data;

generating the first parity code through an Exclusive OR operation of the (n−

1) parts of data;

writing the (n−

1) parts of data into the respective (n−

1) data memories;

reading the (n−

1) parts of data from the respective (n−

1) data memories;

generating the second parity code through an Exclusive OR operation of the (n−

1) parts of data read from the respective (n −

1) data memories; and

comparing the second parity code with the first parity code to generate a result for error finding;

wherein when no error is found according to the result, the (n−

1) parts of data read are blocked to reconstitute the desired data and output the said desired data;

and wherein when an error is found in one of the (n−

1) part of data read according to the result, the error is corrected using the first parity data and the remaining (n−

2) parts of data other than the failed one, and the (n−

1) parts of data read are blocked to reconstitute the desired data.