Padless high density circuit board and manufacturing method thereof

• US 20040169288A1
• Filed: 02/28/2003
• Published: 09/02/2004
• Est. Priority Date: 02/28/2003
• Status: Active Grant

• Current Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Original Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Inventors: Hsieh, Han-Kun, Lin, Wei-Feng
• Granted Patent: US 6,864,586 B2
• Time in Patent Office: Days
• US Class Current: 257/780
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0367 Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/0989 Coating free areas, e.g. areas other than pads or lands free of solder resist
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2203/054 Continuous temporary metal layer over resist, e.g. for selective electroplating
• CPC Class Codes: H05K 2203/0571 Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
• CPC Class Codes: H05K 2203/072 Electroless plating, e.g. finish plating or initial plating
• CPC Class Codes: H05K 2203/0723 Electroplating, e.g. finish plating
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: H05K 3/3473 Plating of solder
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

A padless high density circuit board and manufacturing method thereof. The method includes providing a circuit board substrate having a dielectric layer on a surface, forming external wiring, having a plurality of external terminals with a width as large as or less than the external wiring on the dielectric layer, forming a solder mask over the dielectric layer and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby, and forming a plurality of conductive bumps on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

Claims

1. A padless high density circuit board, comprising:

a circuit board substrate having a dielectric layer on its surface;

external wiring, having a plurality of external terminals with a width as large as or less than the external wiring, formed on the dielectric layer;

a solder mask over the dielectric layer and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby; and

a plurality of conductive bumps formed on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

2. The padless high density circuit board in claim 1, wherein the diameters of the solder mask openings are about 1.2 to 2 times the widths of the external terminals exposed by the solder mask openings.

3. The padless high density circuit board in claim 1, wherein line pitch of the external wiring is approximately 60 μ

m or more.

4. The padless high density circuit board in claim 1, wherein the circuit board substrate is an unfinished laminated circuit board having the dielectric layer on the surface, or the dielectric layer.

5. The padless high density circuit board in claim 1, wherein the external device is an IC chip.

6. The padless high density circuit board in claim 1, wherein the external device is an IC chip, IC package, light-emitting device, connector, passive device, or other PCB.

7. The padless high density circuit board in claim 1, wherein the conductive bumps are formed by electroless plating.

8. The padless high density circuit board in claim 1, wherein the conductive bumps are formed by electroplating.

9. The padless high density circuit board in claim 7, wherein the conductive bumps are Cu, Au coated Ni, Sn—

Pb alloy, or Pb-free, Sn-based alloy.

10. The padless high density circuit board in claim 7, wherein the conductive bumps are not higher than the solder mask.

11. The padless high density circuit board in claim 8, wherein the conductive bumps are Cu, Sn—

Pb alloy coated Cu, Pb-free, Sn-based alloy coated Cu, Au, Sn—

Pb alloy coated Au, Pb-free, Sn-based alloy coated Au, Sn—

Pb alloy, or Pb-free, Sn-based alloy.

12. The padless high density circuit board in claim 8, wherein the conductive bumps are about 20 μ

m to 60 μ

m higher than the solder mask.

13. A padless high density circuit board for connection with an external device with a bump or lead, comprising:

a circuit board substrate having a dielectric layer on a surface;

external wiring, having a plurality of external terminals with a width as large as or less than the external wiring, formed on the dielectric layer;

a solder mask over the dielectric layer and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby; and

a plurality of conductive bumps, not higher than the solder mask, formed on the external terminals exposed by the solder mask openings.

14. The padless high density circuit board in claim 13, wherein the diameters of the solder mask openings are about 1.2 to 2 times the widths of the external terminals exposed by the solder mask openings.

15. The padless high density circuit board in claim 13, wherein line pitch of the external wiring is approximately 60 μ

m or more.

16. The padless high density circuit board in claim 13, wherein the circuit board substrate is an unfinished laminated circuit board having the dielectric layer on the surface or the dielectric layer.

17. The padless high density circuit board in claim 13, wherein the external device is an IC chip, IC package, light-emitting device, connector, passive device, or other PCB.

18. The padless high density circuit board in claim 13, wherein the conductive bumps are Cu, Au coated Ni, Sn—

Pb alloy, or Pb-free, Sn-based alloy.

19. A padless high density circuit board for connection with an external device without a bump or lead, comprising:

a circuit board substrate having a dielectric layer on a surface;

external wiring, having a plurality of external terminals with a width as large as or less than the external wiring, formed on the dielectric layer;

a solder mask over the dielectric layer and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby; and

a plurality of conductive bumps, about 20 μ

m to 60 μ

m higher than the solder mask, formed on the external terminals exposed by the solder mask openings.