Method for setting transistor operating point and circuit therefor, method for changing signal component value and active-matrix liquid crystal display device

• US 20040171221A1
• Filed: 12/03/2003
• Published: 09/02/2004
• Est. Priority Date: 06/04/2001
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: Gold Charm Limited (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Takatori, Ken-ichi
• Granted Patent: US 8,625,038 B2
• Time in Patent Office: Days
• US Class Current: 438/281
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0833 forming a linear amplifier or follower
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A data signal voltage on a signal line 102 is held in a voltage holding capacitor 106 through an n-type MOS transistor 103 switched on by a gate scan voltage, and supplied to an analog amplifier circuit 104-1. The analog amplifier circuit 104-1 is formed of an MOS transistor having a double gate structure, and the operating point thereof is set at an operating range in which dependence of Ids on Vds is substantially nullified. Even when Vds is varied due to a response of liquid crystal 109, Ids is substantially fixed. Accordingly, the pixel voltage which is substantially proportional to the data signal voltage can be applied to the liquid crystal 109.

Claims

1. A method for setting the operating point of a unipolar transistor, wherein in a unipolar transistor having a multi-gate structure equivalently achieved by commonly connecting respective gates of plural unipolar transistors each having a single gate structure and connecting the plural unipolar transistors to one another in series, an operating point of each single unipolar transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range.

2. The method according to claim 1, wherein said unipolar transistor having the multi-gate structure is an insulated gate type transistor having a multi-gate structure or a junction type transistor having a multi-gate structure.

3. The method according to claim 1, wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.

4. The method according to claim 1, wherein said unipolar transistor having the multi-gate structure alters the signal component value of a signal, the signal being any one of an amplified signal, a modulated signal and a demodulated signal.

5. A circuit for setting the operating point of a unipolar transistor, wherein in a unipolar transistor having a multi-gate structure equivalently achieved by commonly connecting respective gates of plural unipolar transistors each having a single gate structure and connecting the plural unipolar transistors to one another in series, an operating point of each single unipolar transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range.

6. The circuit according to claim 5, wherein the unipolar transistor having the multi-gate structure is an insulated gate type transistor having a multi-gate structure or a junction type transistor having a multi-gate structure.

7. The circuit according to claim 5, wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.

8. A method for changing a signal component value of an input signal by using a unipolar transistor, wherein in a unipolar transistor having a multi-gate structure equivalently achieved by commonly connecting respective gates of plural unipolar transistors each having a single gate structure and connecting the plural unipolar transistors to one another in series, an operating point of each single unipolar transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range, and said unipolar transistor having the multi-gate structure is operated at the operating point thus set to change the signal component value of the input signal.

9. The method according to claim 8, wherein the number of said unipolar transistor having the multi-gate structure for which the operating point is set is a singular number or plural number.

10. The method according to claim 8, wherein said unipolar transistor having the multi-gate structure is an insulated gate type transistor having a multi-gate structure or a junction type transistor having a multi-gate structure.

11. The method according to claim 8, wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.

12. The method according to claim 8, wherein the signal is any one of an amplified signal, a modulated signal and a demodulated signal.

13. The method according to claim 8, wherein the signal component of the signal is any one of the amplitude, phase and frequency of the signal.

14. An active-matrix liquid crystal display device, wherein a pixel circuit including a gate circuit, an analog amplifier circuit connected to the output of said gate circuit and liquid crystal connected to the output of said analog amplifier circuit is equipped in the neighborhood of each of the cross points of scan lines and signal lines which are arranged in a matrix form, said gate circuit of said pixel circuit gates a data signal voltage on the signal line corresponding to said pixel circuit to said analog amplifier circuit on the basis of a gate scan voltage on the scan line corresponding to said pixel circuit, and when said analog amplifier circuit applies a pixel voltage to said liquid crystal, said liquid crystal displays the pixel corresponding to the pixel voltage thus applied, said analog amplifier circuit being designed to contain a unipolar transistor having a multi-gate structure.

15. The active-matrix liquid crystal display device according to claim 14, wherein said analog amplifier circuit comprises an amplifier circuit portion and a load element, at least one of said amplifier circuit portion and said load element comprises said unipolar transistor having a multi-gate structure, and the connection point between said amplifier circuit portion and said load element is connected to said liquid crystal.

16. The active-matrix liquid crystal display device according to claim 14, wherein said analog amplifier circuit comprises a differential amplification circuit having two input terminals, a phase compensating circuit having an input terminal connected to the output terminal of said differential amplification circuit, and an output buffer having an input terminal connected to the output terminal of said phase compensating circuit, one of the input terminals of said differential amplification circuit is connected to the output terminal of said gate circuit, the other input terminal of said differential amplification circuit is connected to the output terminal of said output buffer, a constant current supply source of said differential amplification circuit and a current supply source of said output buffer comprise said unipolar transistor having a multi-gate structure, and the output terminal of said output buffer is connected to said liquid crystal.

17. The active-matrix liquid crystal display device according to claim 14, wherein the material of said liquid crystal is nematic liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, thresholdless antiferroelectric liquid crystal, deformed helix ferroelectric liquid crystal, twisted ferroelectric liquid crystal or monostable ferroelectric liquid crystal.

18. The active-matrix liquid crystal display device according to claim 14, wherein said unipolar transistor having a multi-gate structure is an insulated gate type transistor having a multi-gate structure or a junction type transistor having a multi-gate structure.

19. The active-matrix liquid crystal display device according to claim 14, wherein an operating point of said unipolar transistor having a multi-gate structure is set so that in a unipolar transistor having a multi-gate structure equivalently achieved by commonly connecting respective gates of plural unipolar transistors each having a single gate structure and connecting the plural unipolar transistors to one another in series, an operating point of each single unipolar transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range.

20. The active-matrix liquid crystal display device according to claim 19, wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.

21. The active-matrix liquid crystal display device according to claim 15, wherein said load element comprises said unipolar transistor having a multi-gate structure, and the value of the source-drain resistance of said unipolar transistor is set at not more than the value of a resistance component determining the response time constant of said liquid crystal.

22. The active-matrix liquid crystal display device according to claim 21, wherein the setting is carried out by setting the gate-source voltage of said unipolar transistor having a multi-gate structure constituting said load element to a voltage at which the value of the source-drain resistance of said unipolar transistor is not more than the value of the resistance component determining the response time constant of said liquid crystal.

23. The active-matrix liquid crystal display device according to claim 21, wherein when the gate and source electrodes of said unipolar transistor having a multi-gate structure constituting said load element are connected to each other, at the manufacturing time of said unipolar transistor, a threshold voltage value of said unipolar transistor is shifted, by channel dose, to a voltage at which the value of the source-drain resistance of said unipolar transistor is not more than the value of the resistance component determining the response time constant of said liquid crystal, whereby the setting is carried out.

24. The active-matrix liquid crystal display device according to claim 21, wherein said load element is a resistor, and the value of said resistor is set at not more than the value of a resistance component determining the response time constant of said liquid crystal.

25. The active-matrix liquid crystal display device according to claim 24, wherein said resistor is formed of a semiconductor thin film or a semiconductor thin film doped with impurities.

26. The active-matrix liquid crystal display device according to claim 15, wherein a driving signal for said unipolar transistor constituting said amplifier circuit portion of each of pixel circuits is a gate scan voltage used for scanning of the just preceding pixel circuit to the pixel circuit concerned in the scanning order of an image to be displayed.

27. The active-matrix liquid crystal display device according to claim 15, wherein said unipolar transistor constituting said amplifier circuit portion of each of the pixel circuits is a p-type unipolar transistor or n-type unipolar transistor, and a driving signal for said unipolar transistor constituting said amplifier circuit portion is a reset pulse output from a reset pulse power supply source when a scanning turn of the pixel circuit concerned in the scanning order of an image to be displayed comes.

28. The active-matrix liquid crystal display device according to claim 15, wherein all of said unipolar transistors constituting said gate circuit and said amplifier circuit portion of each of the pixel circuits are formed of p-type unipolar transistors or n-type unipolar transistors, and a driving signal for said unipolar transistor constituting said amplifier circuit portion is a reset pulse output from a reset pulse power supply source when a scanning turn of the pixel circuit concerned in the scanning order of an image to be displayed comes.

29. The active-matrix liquid crystal display device according to claim 27, wherein a gate scan voltage for making said gate circuit of each of the pixel circuits operate and a reset pulse voltage for making said amplifier circuit portion of each of the pixel circuits operate are supplied simultaneously.

30. The active-matrix liquid crystal display device according to claim 28, wherein said unipolar transistors constituting said gate circuit and said amplifier circuit portion of each of the pixel circuits are formed of thin film unipolar transistors.

31. The active-matrix liquid crystal display device according to claim 15, wherein all of said unipolar transistors constituting said gate circuit and said amplifier circuit portion of each of the pixel circuits are designed to have a multi-gate structure.

32. The active-matrix liquid crystal display device according to claim 16, wherein a constant current supply source of said differential amplification circuit and a current supply source of said output buffer are constructed by unipolar transistors having the multi-gate structure.

33. The active-matrix liquid crystal display device according to claim 16, wherein each of other parts than a constant current supply source of said differential amplification circuit and/or each of other parts than said output buffer are constructed by unipolar transistors having the multi-gate structure.

34. The active-matrix liquid crystal display device according to claim 14, wherein said liquid crystal is driven while switching the color of light incident to said liquid crystal during one-field period or one-frame period, thereby performing color display.