Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section

• US 20040172569A1
• Filed: 02/27/2003
• Published: 09/02/2004
• Est. Priority Date: 02/27/2003
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Faue, Jon Allan, Meadows, Harold Brett
• Granted Patent: US 7,039,822 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Claims

1. An integrated circuit device incorporating a plurality of memory arrays located intermediate an address generation block and a data output block, said device comprising:

an address bus extending from said address generation block to each of said memory arrays for accessing selected data therein;

a data bus extending from each of said memory arrays to said data output block for providing said selected data thereto; and

signal delay elements selectively interposed on said address and data buses between preselected ones of said plurality of memory arrays such that a cumulative number of signal delays on both said address and data buses from said address generation block to said data output block is substantially a constant for each of said plurality of memory arrays.

2. The integrated circuit device of claim 1 further comprising:

a clock generation block in association with said address generation block;

a clock bus extending between said clock generation block and said data output block; and

additional signal delay elements selectively interposed on said clock bus between preselected ones of said plurality of memory arrays such that a cumulative number of signal delays on said clock bus equals said constant.

3. The integrated circuit device of claim 1 wherein said signal delay elements comprise inverter pairs.

4. The integrated circuit device of claim 3 wherein said inverter pairs comprise CMOS inverters.

5. The integrated circuit device of claim 1 wherein said signal delay elements comprise non-inverting drivers.

6. The integrated circuit device of claim 1 further comprising a tri-state driver interposed between each of said plurality of memory arrays and said data bus.

7. The integrated circuit device of claim 1 wherein at least one of said signal delay elements interposed between said preselected ones of said plurality of memory arrays on said data bus comprises a tri-state driver.

8. The integrated circuit device of claim 1 wherein at least a portion of said plurality of memory arrays are each arranged into a pair of banks laterally opposite each other from said address and data buses.

9. The integrated circuit device of claim 1 wherein said plurality of memory arrays comprise dynamic random access memory.

10. The integrated circuit device of claim 9 wherein said plurality of memory arrays comprise synchronous dynamic random access memory.

11. A method for minimizing skew between address, clock and data signals on respective address, clock and data buses extending between an address/clock generation block and a data output block in an integrated circuit memory device, said method comprising:

selectively placing a first predetermined number of signal delays on said address and clock buses between said address/clock generation block and each of preselected ones of memory arrays of said memory device coupled to said data bus; and

selectively placing a second predetermined number of signal delays on said data bus between each of said preselected ones of said memory arrays such that a total of said first and second predetermined number of said signal delays on said address, clock and data buses from said address/clock generation block to said data output block is substantially a constant for each of said memory arrays.

12. The method of claim 11 wherein said steps of selectively placing said first and second predetermined number of signal delays are carried out by series coupled signal inverter pairs.

13. The method of claim 11 wherein said steps of selectively placing said first and second predetermined number of signal delays are carried out by non-inverting drivers.

14. The method of claim 11 wherein said step of selectively placing said second predetermined number of signal delays is carried out by:

providing a tri-state driver for each of said second predetermined number of signal delays.

15. The method of claim 11 further comprising:

providing a tri-state driver for coupling each of said preselected ones of said memory arrays to said data bus.

16. The method of claim 11 wherein said first predetermined number of signal delays is one more than said second predetermined number of signal delays.

17. The method of claim 11 further comprising:

partitioning each of said memory arrays into a plurality of memory banks; and

placing each of said plurality of memory banks on laterally opposite sides of said data bus.

18. An integrated circuit device comprising:

N memory arrays;

an address bus coupling an address generation block to each of said N memory arrays;

a data bus coupling each of said N memory arrays to a data output block;

a signal delay interposed on said address bus between said address generation block and each of said N memory arrays; and

a signal delay interposed on said data bus between each of said N memory arrays such that each of said memory arrays present a cumulative delay to address and data signals on said address and data buses between said address generation and data output blocks of substantially N signal delays.

19. The integrated circuit device of claim 18 further comprising:

a clock generation block in association with said address generation block;

a clock bus extending between said clock generation block and said data output block;

a signal delay interposed on said clock bus between said clock generation block and each of said N memory arrays.

20. The integrated circuit device of claim 18 wherein said signal delays comprise inverter pairs.

21. The integrated circuit device of claim 20 wherein said inverter pairs comprise CMOS inverters.

22. The integrated circuit device of claim 18 wherein said signal delays comprise non-inverting drivers.

23. The integrated circuit device of claim 18 further comprising:

a tri-state driver interposed between each of said N memory arrays and said data bus.

24. The integrated circuit device of claim 18 wherein at least one of said signal delays interposed between each of said N memory arrays on said data bus comprise a tri-state driver.

25. The integrated circuit device of claim 18 wherein at least a portion of said N memory arrays are each arranged into a pair of banks laterally opposite each other from said data bus.

26. The integrated circuit device of claim 18 wherein said N memory arrays comprise dynamic random access memory.

27. The integrated circuit device of claim 26 wherein said N memory arrays comprise synchronous random access memory.

28. A technique for minimizing skew between clock and data signals at a data output block of an integrated circuit memory device comprising a plurality of memory arrays, said technique comprising:

selectively adding delays to address and clock information buses coupled to said memory arrays such that a cumulative delay to signals generated on said address and clock information buses increases as a position of each of said memory arrays becomes more distal from an address/clock generation block; and

selectively adding delays to a data bus coupled to said memory arrays such that a cumulative delay to signals output on said data bus decreases as a position of each of said memory arrays becomes more proximate to said data output block such that a total delay added to said address, clock information and data buses for each of said memory arrays is substantially constant.