Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section
First Claim
1. An integrated circuit device incorporating a plurality of memory arrays located intermediate an address generation block and a data output block, said device comprising:
- an address bus extending from said address generation block to each of said memory arrays for accessing selected data therein;
a data bus extending from each of said memory arrays to said data output block for providing said selected data thereto; and
signal delay elements selectively interposed on said address and data buses between preselected ones of said plurality of memory arrays such that a cumulative number of signal delays on both said address and data buses from said address generation block to said data output block is substantially a constant for each of said plurality of memory arrays.
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Accused Products
Abstract
An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.
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Citations
28 Claims
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1. An integrated circuit device incorporating a plurality of memory arrays located intermediate an address generation block and a data output block, said device comprising:
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an address bus extending from said address generation block to each of said memory arrays for accessing selected data therein;
a data bus extending from each of said memory arrays to said data output block for providing said selected data thereto; and
signal delay elements selectively interposed on said address and data buses between preselected ones of said plurality of memory arrays such that a cumulative number of signal delays on both said address and data buses from said address generation block to said data output block is substantially a constant for each of said plurality of memory arrays. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for minimizing skew between address, clock and data signals on respective address, clock and data buses extending between an address/clock generation block and a data output block in an integrated circuit memory device, said method comprising:
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selectively placing a first predetermined number of signal delays on said address and clock buses between said address/clock generation block and each of preselected ones of memory arrays of said memory device coupled to said data bus; and
selectively placing a second predetermined number of signal delays on said data bus between each of said preselected ones of said memory arrays such that a total of said first and second predetermined number of said signal delays on said address, clock and data buses from said address/clock generation block to said data output block is substantially a constant for each of said memory arrays. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An integrated circuit device comprising:
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N memory arrays;
an address bus coupling an address generation block to each of said N memory arrays;
a data bus coupling each of said N memory arrays to a data output block;
a signal delay interposed on said address bus between said address generation block and each of said N memory arrays; and
a signal delay interposed on said data bus between each of said N memory arrays such that each of said memory arrays present a cumulative delay to address and data signals on said address and data buses between said address generation and data output blocks of substantially N signal delays. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A technique for minimizing skew between clock and data signals at a data output block of an integrated circuit memory device comprising a plurality of memory arrays, said technique comprising:
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selectively adding delays to address and clock information buses coupled to said memory arrays such that a cumulative delay to signals generated on said address and clock information buses increases as a position of each of said memory arrays becomes more distal from an address/clock generation block; and
selectively adding delays to a data bus coupled to said memory arrays such that a cumulative delay to signals output on said data bus decreases as a position of each of said memory arrays becomes more proximate to said data output block such that a total delay added to said address, clock information and data buses for each of said memory arrays is substantially constant.
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Specification