Methods for manufacturing semiconductor devices and semiconductor devices

• US 20040173833A1
• Filed: 03/22/2004
• Published: 09/09/2004
• Est. Priority Date: 01/13/2000
• Status: Active Grant

• Current Assignee: Hiroaki Tsugane, Hisakatsu Sato
• Original Assignee: Hiroaki Tsugane, Hisakatsu Sato
• Inventors: Sato, Hisakatsu, Tsugane, Hiroaki
• Granted Patent: US 6,982,466 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

Embodiments of the present invention include a method for manufacturing a semiconductor device and a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N⁺ type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Claims

1. A semiconductor device comprising:

a DRAM located in a memory cell region; and

a field effect transistor located in a field effect transistor region that is a region other than the memory cell region,

wherein silicide layers are formed at a cell plate that is a component of a capacitor of the DRAM and at a source/drain that is a component of the field effect transistor, and

silicide layers are not formed at a source/drain that is a component of a memory cell selection field effect transistor of the DRAM.

2. A semiconductor device according to claim 1, further comprising:

a silicide wiring layer;

the silicide wiring layer being connected to the source/drain of the field effect transistor, and

the silicide wiring layer being located in a common layer where the silicide layers at the source/drain of the field effect transistor are located.

3. A semiconductor device according to claim 1, further comprising:

an additional a field effect transistor located in a region other than the memory cell region, the additional field effect transistor including source/drain regions, wherein silicide layers are formed at the source/drain regions of the additional field effect transistor.

4. A semiconductor device according to claim 3, wherein a silicide layer at one of the source/drain regions of the field effect transistor extends to a position at one of the source/drain regions of the additional field effect transistor.

5. A semiconductor device comprising:

a DRAM located in a memory cell region;

a first field effect transistor that is located in a peripheral circuit region and becomes a component of a peripheral circuit for the DRAM; and

a second field effect transistor located in a region other than the memory cell region and the peripheral circuit region,

wherein silicide layers are formed at a cell plate that is a component of a capacitor of the DRAM and at a source/drain of the second field effect transistor, and

silicide layers are not formed at a source/drain that is a component of a memory cell selection field effect transistor of the DRAM or at a source/drain of the first field effect transistor.

6. A semiconductor device comprising;

a memory cell region including a DRAM, the DRAM including a memory cell selection field effect transistor and source/drain regions, the DRAM also including a capacitor, the capacitor including first and second capacitor electrodes and a dielectric layer therebetween;

a peripheral circuit region having a peripheral circuit field effect transistor and source/drain regions therein,

a logic circuit region having a logic circuit field effect transistor and source/drain regions therein,

wherein the source/drain regions of the logic circuit field effect transistor are in direct contact with a silicide material; and

wherein the source/drain regions of the memory cell selection field effect transistor are not in direct contact with a silicide material.

7. A semiconductor device as in claim 6, wherein one of the first and second capacitor electrodes is in direct contact with a silicide material.

8. A semiconductor device as in claim 6, wherein the source/drain regions in the peripheral circuit region are in direct contact with a silicide material.

9. A semiconductor device as in claim 6, wherein the source/drain regions in the peripheral circuit region are not in direct contact with a silicide layer.

10. A semiconductor device as in claim 7, wherein the source/drain regions in the peripheral circuit region are in direct contact with a silicide material.

11. A semiconductor device as in claim 7, wherein the source/drain regions in the peripheral circuit region are not in direct contact with a silicide layer.

12. A semiconductor device as in claim 6, further comprising an additional logic circuit field effect transistor, the additional logic circuit field effect transistor including source/drain regions that are in direct contact with a silicide material.

13. A semiconductor device as in claim 7, further comprising an additional logic circuit field effect transistor, the additional logic circuit field effect transistor including source/drain regions that are in direct contact with a silicide material.

14. A semiconductor device as in claim 12, wherein silicide material in direct contact with one of the source/drain regions of the logic circuit field effect transistor is connected to the silicide material in direct contact with one of the source/drain regions of the additional logic field effect transistor.

15. A semiconductor device as in claim 12, wherein a field oxide region is positioned between the logic circuit field effect transistor and the additional logic circuit field effect transistor, and a silicide material extends over the field oxide region between logic circuit field effect transistor and the additional logic circuit field effect transistor.

16. A semiconductor device as in claim 13, wherein a field oxide region is positioned between the logic circuit field effect transistor and the additional logic circuit field effect transistor, and a silicide material extends over the field oxide region between logic circuit field effect transistor and the additional logic circuit field effect transistor.

17. A semiconductor device as in claim 6, wherein the DRAM in the memory cell region includes including an additional memory cell selection field effect transistor and source/drain regions, wherein the source/drain regions of the additional memory cell selection field effect transistor are not in direct contact with a silicide layer.

18. A semiconductor device as in claim 7, wherein the DRAM in the memory cell region includes including an additional memory cell selection field effect transistor and source/drain regions, wherein the source/drain regions of the additional memory cell selection field effect transistor are not in direct contact with a silicide layer.