Trench power MOSFET with planarized gate bus

• US 20040173844A1
• Filed: 03/05/2003
• Published: 09/09/2004
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Granted Patent: US 6,861,701 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Claims

1. A power MOSFET comprising:

a substrate comprising a first trench and a second trench extending from a top surface of the substrate;

a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;

a gate structure that extends continuously in the first and second trenches, wherein a top surface of the gate structure does not extend above the top surface of the substrate, a first portion of the gate structure acts as a gate of a vertical device in the wall of the first trench, and a second portion of the gate structure resides in the second trench; and

a gate contact that contacts the second portion of the gate structure.

2. The power MOSFET of claim 1, wherein the second trench is wider than the first trench.

3. The power MOSFET of claim 1, wherein the first trench is deeper that the second trench.

4. The power MOSFET of claim 1, further comprising a dielectric material residing in the first and second trenches above the gate structure, wherein a top surface of the dielectric material is coplanar with the top surface of the substrate.

5. The power MOSFET of claim 1, further comprising a metal layer that is patterned to form a source contact that overlies the first trench and contacts the source region adjacent to the first trench and the gate contact that contacts the gate structure in the second trench.

6. The power MOSFET of claim 1, wherein the gate structure comprises a continuous polysilicon region that extends from the first trench to the second trench.

7. The power MOSFET of claim 6, wherein the gate structure further comprises a metal/silicide region in the first trench.

8. The power MOSFET of claim 7, wherein the polysilicon region in the surrounds the metal/silicide region and prevents direct contact between the metal/silicide and a gate oxide region.

9. The power MOSFET of claim 6, wherein the gate structure further comprises a metal/silicide region in the second trench.

10. The power MOSFET of claim 9, wherein the metal/silicide region extends continuously from the second trench into the first trench.

11. A fabrication process for a power MOSFET comprising:

forming a first trench in a substrate;

forming a second trench in the substrate;

forming a conductive gate structure that extends continuously from the first trench into the second trench;

doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench;

performing a chemical mechanical polishing (CMP) process on a structure including the conductive gate structure in the first and second trenches; and

depositing a contact layer after the CMP process, wherein the contact layer includes a first region contacting the device adjacent to the first trench and a second region overlying the second trench and contacting the conductive gate structure.

12. The fabrication process of claim 11, further comprising forming an insulating layer overlying the conductive gate structure.

13. The fabrication process of claim 12, wherein the CMP process removes the insulating layer from above the mesa.

16. The fabrication process of claim 12, further comprising:

forming a hardmask having openings that define boundaries of the first and second trenches, wherein the CMP process exposes a region of the hardmask overlying the mesa and leaves the regions of the insulating layer in the openings in the hardmask; and

removing the hardmask without removing the regions of the insulating layer left after the CMP process, wherein the contact layer contacts the mesa where the region of the hardmask was removed and the regions of the insulating layer separate the gate structure in the first trench from the contact layer.

17. The fabrication process of claim 11, further comprising forming a layer of a hardmask material on the substrate, wherein forming the second trench comprises patterning the hardmask material to form an opening over an area of the substrate corresponding to the second trench.

18. The fabrication process of claim 17, wherein forming the second trench comprises:

performing a LOCOS operation to oxidize the substrate in the area of the opening in the hardmask material; and

removing an oxide region formed during the LOCOS operation to leave the second trench in the substrate.

19. The fabrication process of claim 17, further comprising etching the substrate exposed through the opening in the hardmask material to thereby form the second trench.

14. The fabrication process of claim 14, further comprising performing a contact etch that etches an opening through the insulating layer to expose a portion of the conductive gate structure in the second trench, the contact layer filling the opening and contacting the exposed portion of the gate structure in the second trench.

15. The fabrication process of claim 14, performing the contact etch forms a second opening through the insulating layer that exposes the mesa, the contact layer filling the second opening and contacting the vertical device.

20. The fabrication process of claim 15, wherein the second trench is wider than the first trench.