Semiconductor device having gate insulating layers with differing thicknesses and methods of fabricating the same
First Claim
1. A semiconductor device comprising:
- a first gate pattern on a first active area of a semiconductor substrate, the first gate pattern having a top width that is substantially the same as or less than a bottom width of the first gate pattern; and
a second gate pattern on a second active area of the semiconductor substrate, the second gate pattern having a top width that is wider than a bottom width of the second gate pattern.
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Accused Products
Abstract
Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.
14 Citations
18 Claims
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1. A semiconductor device comprising:
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a first gate pattern on a first active area of a semiconductor substrate, the first gate pattern having a top width that is substantially the same as or less than a bottom width of the first gate pattern; and
a second gate pattern on a second active area of the semiconductor substrate, the second gate pattern having a top width that is wider than a bottom width of the second gate pattern. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a semiconductor device comprising:
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forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate;
forming a mask insulation layer on the semiconductor substrate that includes the first gate pattern;
forming first and second gate openings respectively exposing second and third active regions of the semiconductor substrate by patterning the mask insulation layer;
forming second and third gate insulation layers respectively on second and third active regions exposed in the first and second gate openings;
forming second and third gate patterns in the first and second gate openings respectively; and
removing the mask insulation layer. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method of fabricating a semiconductor device comprising:
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forming a first gate pattern on a first active area of a semiconductor substrate, the first gate pattern having a top width that is substantially the same as or less than a bottom width of the first gate pattern; and
forming a second gate pattern on a second active area of the semiconductor substrate, the second gate pattern having a top width that is wider than a bottom width of the second gate pattern. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification