Semiconductor device having gate insulating layers with differing thicknesses and methods of fabricating the same

• US 20040173854A1
• Filed: 03/05/2004
• Published: 09/09/2004
• Est. Priority Date: 03/06/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Soon-Moon, Kwon, Hyung-Shin
• Granted Patent: US 7,151,031 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

Claims

1. A semiconductor device comprising:

a first gate pattern on a first active area of a semiconductor substrate, the first gate pattern having a top width that is substantially the same as or less than a bottom width of the first gate pattern; and

a second gate pattern on a second active area of the semiconductor substrate, the second gate pattern having a top width that is wider than a bottom width of the second gate pattern.

2. The semiconductor device of claim 1, further comprising a third gate pattern on a third active area of the semiconductor substrate, the third gate pattern having a top width that is wider than a bottom width of the third gate pattern.

3. The semiconductor device of claim 2, further comprising:

a first gate insulating layer disposed between the first gate pattern and the first active area and having a first thickness;

a second gate insulating layer disposed between the second gate pattern and the second active area and having a second thickness that is greater than the first thickness of the first gate insulating layer; and

a third gate insulating layer disposed between the third gate pattern and the third active area and having a third thickness that is greater than the second thickness of the second gate insulating layer.

4. The semiconductor device of claim 2, further comprising respective silicide layers on the first gate pattern, the second gate pattern and the third gate pattern.

5. The semiconductor device of claim 2, further comprising impurity diffusion regions in respective ones of the first, second and third active regions adjacent sides of the first, second and third gate patterns.

6. The semiconductor device of claim 2, wherein the second and third gate patterns further comprise:

a conductive adhesion layer having a substantially “

U”

shaped cross section; and

a metal layer in a gap region of the conductive adhesion layer.

7. A method of fabricating a semiconductor device comprising:

forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate;

forming a mask insulation layer on the semiconductor substrate that includes the first gate pattern;

forming first and second gate openings respectively exposing second and third active regions of the semiconductor substrate by patterning the mask insulation layer;

forming second and third gate insulation layers respectively on second and third active regions exposed in the first and second gate openings;

forming second and third gate patterns in the first and second gate openings respectively; and

removing the mask insulation layer.

8. The method of fabricating a semiconductor device according to claim 7, wherein a top width of the first and second gate openings is wider than a bottom width of the first and second gate openings.

9. The method of fabricating a semiconductor device according to claim 7, wherein forming second and third gate insulation layers further comprises:

forming a first insulation layer on the semiconductor substrate in the first and second gate openings;

exposing the second active region in the first gate opening by removing the first insulation layer in the first gate opening; and

forming a second insulation layer on the semiconductor substrate including on the second active region exposed by the first gate opening to provide the second gate insulation layer.

10. The method of fabricating a semiconductor device according to claim 9, wherein forming a second insulation layer on the semiconductor substrate further comprises forming a second insulation layer on the semiconductor substrate including on the first insulation layer in the second gate opening to provide the third gate insulation layer comprising the first insulation layer and the second insulation layer in the second gate opening.

11. The method of fabricating a semiconductor device according to claim 8, wherein the mask insulation layer is conformally formed, and wherein forming the first and second gate openings comprises:

forming a photoresist layer on the mask insulation layer;

removing an upper portion of the photoresist layer to expose the mask insulation layer on the first gate pattern;

patterning the photoresist layer to expose a portion of the mask insulation layer corresponding to the first and second gate openings; and

etching the mask insulation layer using the photoresist layer as an etching mask.

12. The method of fabricating a semiconductor device according to claim 7, wherein forming the second and third gate patterns comprises:

forming a conductive adhesion layer on the semiconductor substrate including on the second and third gate insulation layers in the first and second gate openings;

forming a metal layer on the conductive adhesion layer; and

planarizing the metal layer and the conductive adhesion layer to form the second and third gate patterns in the first and second gate openings.

13. A method of fabricating a semiconductor device comprising:

forming a first gate pattern on a first active area of a semiconductor substrate, the first gate pattern having a top width that is substantially the same as or less than a bottom width of the first gate pattern; and

forming a second gate pattern on a second active area of the semiconductor substrate, the second gate pattern having a top width that is wider than a bottom width of the second gate pattern.

14. The method of fabricating a semiconductor device according to claim 13, further comprising forming a third gate pattern on a third active area of the semiconductor substrate, the third gate pattern having a top width that is wider than a bottom width of the third gate pattern.

15. The method of fabricating a semiconductor device according to claim 14, further comprising:

forming a first gate insulating layer disposed between the first gate pattern and the first active area and having a first thickness;

forming a second gate insulating layer disposed between the second gate pattern and the second active area and having a second thickness that is greater than the first thickness of the first gate insulating layer; and

forming a third gate insulating layer disposed between the third gate pattern and the third active area and having a third thickness that is greater than the second thickness of the second gate insulating layer.

16. The method of fabricating a semiconductor device according to claim 14, further comprising forming respective silicide layers on the first gate pattern, the second gate pattern and the third gate pattern.

17. The method of fabricating a semiconductor device according to claim 14, further comprising forming impurity diffusion regions in respective ones of the first, second and third active regions adjacent sides of the first, second and third gate patterns.

18. The method of fabricating a semiconductor device according to claim 14, wherein forming the second and third gate patterns further comprise:

forming a conductive adhesion layer having a substantially “

U”

shaped cross section; and

forming a metal layer in a gap region of the conductive adhesion layer.