High frame rate high definition imaging system and method

• US 20040174439A1
• Filed: 03/04/2004
• Published: 09/09/2004
• Est. Priority Date: 03/07/2003
• Status: Active Grant

• Current Assignee: Iconix Video, Inc.
• Original Assignee: Iconix Video, Inc.
• Inventors: Upton, Wayne A.
• Granted Patent: US 8,218,052 B2
• Time in Patent Office: Days
• US Class Current: 348/222.1
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A high frame rate high definition imaging system and method are disclosed. An imager is clocked asynchronously to a desired output video clock. During a frame cycle, data held in a first portion of the pixel array in the imager is clocked out of the imager using an imager clock signal, and data held in a second portion of the pixel array is bypassed. The imager data is subsequently converted to a higher video clock rate and output as desired video data.

Claims

1. An imaging system, comprising:

a timing generator providing an imager clock signal having an imager clock rate and a video clock signal having a video clock rate greater than the imager clock rate;

an imager having an imager clock input receiving the imager clock signal and a data output; and

a rate converter, coupled to the data output of the imager and to the timing generator and receiving the imager clock signal and the video clock signal, the rate converter receiving imager data at a rate synchronous to the imager clock rate and outputting video data at the video clock rate.

2. The imaging system of claim 1, wherein the imager comprises a pixel array holding pixel data representative of an image captured by the imager, the pixel array having a first portion and a second portion.

3. The imaging system of claim 2, wherein the timing generator generates a sequence of timing signals to control the imager to skip over the second portion of the pixel array and clock the first portion of the pixel array from the imager to the rate converter.

4. The imaging system of claim 3, wherein the timing generator generates horizontal timing pulses and vertical timing pulses, and wherein the horizontal timing pulses correspond to the imager clock rate.

5. The imaging system of claim 1, wherein the imager clock signal and video clock signal are asynchronous to one another.

6. The imaging system of claim 3, wherein the first portion of the pixel array comprises desired active pixels.

7. The imaging system of claim 6, wherein the second portion of the pixel array comprises inactive or dummy pixels.

8. The imaging system of claim 3, wherein the second portion of the pixel array comprises a combination of undesired active pixels and inactive pixels, and the first portion comprises desired active pixels of the pixel array.

9. The imaging system of claim 3, wherein the imager is a CCD sensor and electric charge is accumulated by the imager for the pixels of the pixel array, and wherein the electric charge associated with the second portion of the pixel array is shifted out of the imager simultaneously for groups of plural rows.

10. The imaging system of claim 9, wherein one or more horizontal and vertical timing pulses control the accumulation of electric charge in a transfer portion of the imager and the horizontal transfer clock controls the transfer of charge corresponding to plural rows of pixel data out of the imager simultaneously.

11. The imaging system of claim 1, wherein the timing generator comprises:

an imager clock generator circuit block outputting an imager clock;

a video clock generator circuit block outputting a video clock;

a master synchronization circuit block; and

an imager timing logic block, coupled to the imager clock generator and master synchronization circuit blocks and outputting said imager clock signal at the imager clock rate.

12. The imaging system of claim 11, wherein the master synchronization circuit block is coupled to the video clock generator circuit block and receives the video clock.

13. The imaging system of claim 1, wherein the rate converter comprises a memory for receiving and temporarily storing image data from the imager and rate converter control logic.

14. The imaging system of claim 13, wherein the rate converter control logic comprises a memory control circuit for controlling the writing and reading of data to and from the memory.

15. The imaging system of claim 14, wherein the memory control circuit is coupled to the timing generator and receives a signal synchronous the imager clock signal and the video clock signal.

16. The imaging system of claim 15, wherein the rate converter control logic further comprises video timing logic coupled to the memory control circuit and to the timing generator and receiving the video clock signal, wherein the video timing logic controls the memory control circuit to interrupt read out of data from the memory during blanking intervals of the output video data.

17. The imaging system of claim 16, wherein the rate converter control logic further comprises a video output generator coupled to the memory and the video timing logic, wherein the video output generator receives output video data from the memory and inserts blanking data during blanking intervals during which the read out of the memory is suspended and outputs video data with actual pixel data and blanking data at the video clock rate.

18. The imaging system of claim 17, wherein the output video data is provided in a VESA standard timing.

19. The imaging system of claim 17, wherein the output video data is provided in a SMPTE HDTV standard timing.

20. An increased frame rate imaging system, comprising:

an image sensor having an array of pixels, including inactive pixels, an output for providing image data, and one or more control inputs for receiving read out timing control signals; and

a timing generator providing timing pulses to the control inputs of the image sensor to control the read out of the image sensor to skip over at least some of the inactive pixels of the pixel array, and clock out image data from a desired portion of the pixel array, thereby effectively increasing the frame rate of the image sensor.

21. The increased frame rate imaging system of claim 20, wherein the timing pulses comprise vertical and horizontal timing pulses including a series of consecutive vertical transfer pulses to skip over plural rows of dummy and/or reference and/or unwanted active pixels of the pixel array.

22. The increased frame rate imaging system of claim 20, wherein the timing pulses comprise vertical and horizontal timing pulses including a vertical transfer pulse prior to the end of a line of a desired portion of the pixel array to skip over plural dummy and/or reference, and/or unwanted active pixels at the end of the line.

23. The increased frame rate imaging system of claim 20, wherein the image sensor is a CCD imager and comprises an accumulation area and a transfer area associated with the pixel array.

24. The increased frame rate imaging system of claim 23, wherein the timing pulses comprise vertical and horizontal timing pulses to transfer the image data from the accumulation area to the transfer area and subsequently out of the imager and wherein plural rows of unused pixel data are transferred into the horizontal transfer area using said vertical timing pulses and clocked out together using said horizontal timing pulses.

25. A method of providing high definition video data using an imager operating at a lower clock rate, comprising:

clocking image data from the imager using an imager clock signal at an imager clock rate; and

converting the imager data to video data at a video clock rate greater than the imager clock rate.

26. The method of claim 25, wherein converting the imager data to video data comprises buffering the image data in a memory.

27. The method of claim 26, wherein converting the imager data to video data further comprises writing imager data into the memory at a rate synchronous to the imager clock rate, and reading the data out of the memory at a different clock rate.

28. The method of claim 27, wherein converting the imager data to video data further comprises inserting blanking data, corresponding to blanking intervals of the video data, into the imager data.

29. The method of claim 28, wherein converting the imager data to video data further comprises suspending read out of data from the memory during said inserting of blanking pixel data.

30. The method of claim 25, wherein the imager clock signal is asynchronous to the video data.

31. The method of claim 30, wherein the video data is output in a VESA standard timing.

32. The method of claim 30, wherein the video data is output in a SMPTE HDTV standard timing.

33. A method of increasing the frame rate of an imager having a pixel array with first and second portions, the method comprising:

skipping over the second portion of the pixel array; and

clocking image data held in the first portion of the pixel array from the imager using imager control timing signals.

34. The method of increasing the frame rate of an imager of claim 33, wherein skipping over the second portion of the pixel array comprises providing a series of consecutive vertical transfer pulses to the imager to skip over plural rows of image data in the second portion.

35. The method of increasing the frame rate of an imager of claim 33, wherein skipping over the second portion of the pixel array comprises providing a vertical transfer pulse prior to the end of a line of the pixel array to skip over pixels at the end of the line.

36. The method of increasing the frame rate of an imager of claim 33, wherein the first portion of the pixel array comprises the desired active and desired inactive pixels and the second portion of the pixel array comprises inactive pixels and any undesired active pixels.

37. The method of increasing the frame rate of an imager of claim 36, wherein the inactive pixels generally correspond with blanking intervals of a standard video timing scheme.

38. The method of increasing the frame rate of an imager of claim 37, wherein the standard video timing scheme is a VESA standard timing.

39. The method of increasing the frame rate of an imager of claim 37, wherein the standard video timing scheme is a SMPTE HDTV standard timing.

40. The method of increasing the frame rate of an imager of claim 33, wherein the imager is a CCD imager and wherein the method further comprises clocking out charge corresponding to the second portion of the pixel array.