Programmable reference for 1T/1C ferroelectric memories

• US 20040174750A1
• Filed: 06/05/2003
• Published: 09/09/2004
• Est. Priority Date: 03/07/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Moise, Theodore S., McAdams, Hugh, Summerfelt, Scott, Kraus, Bill, Eliason, Jarrod
• Granted Patent: US 6,819,601 B2
• Time in Patent Office: Days
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Claims

1. A memory device, comprising:

a logic programmable capacitance reference circuit adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions;

a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage; and

a sense circuit coupled to the bit line pair, and operable to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

2. The memory of claim 1, wherein the one or more memory conditions comprises one of an after-pulse sense technique and an on-pulse sense technique.

3. The memory of claim 1, wherein the one or more memory conditions comprises a temperature associated with the memory.

4. The memory of claim 1, wherein the one or more memory conditions comprises one of a location of the ferroelectric capacitor on a semiconductor die and a location of the die on a semiconductor wafer.

5. The memory of claim 1, wherein the one or more memory conditions comprises characterization data associated with the ferroelectric capacitor.

6. The memory of claim 1, wherein the logic programmable capacitance reference circuit further comprises:

a reference control circuit configured to receive one or more input signals associated with the one or more memory conditions and generate one or more output signals in response thereto;

a variable capacitance reference circuit coupled to the reference control circuit and receiving the one or more output signals thereof, operable to generate a capacitance having a value that is a function of the one or more output signals of the reference control circuit,

wherein the capacitance of the variable capacitance reference circuit couples to one of the bit lines in the bit line pair and forms a capacitive divider therewith, thereby defining the reference voltage.

7. The memory of claim 6, further comprising a plurality of bit line pairs collectively forming a memory block, wherein the capacitance of the variable capacitance reference circuit couples to one of the bit lines in each of the plurality of bit lines pairs and forms a shared capacitive divider therewith, thereby defining the reference voltage that serves as a shared reference voltage for each of the bit line pairs.

8. The memory of claim 6, wherein the variable capacitance reference circuit further comprises a plurality of capacitive loading circuits selectively coupled together to an output node, wherein each of the capacitive loading circuits are connected to the output node based on a state of the one or more output signals, wherein a number of the plurality of capacitive loading circuit coupled together to the output node defines an amount of capacitance thereon.

9. A ferroelecteric memory, comprising:

an array of ferroelectric memory cells organized in a 1T1C type architecture having a plurality of bit line pairs;

a sense amplifier circuit selectively coupled across the pair of bit lines, and operable to generate an output state based on a voltage difference between the pair of bit lines; and

a logic programmable capacitance reference circuit selectively coupled to one of the pair of bit lines, and operable to generate a reference voltage during a sense mode of operation, wherein a value of the reference voltage is variable and a function of one or more memory conditions.

10. The ferroelectric memory of claim 9, wherein the logic programmable capacitance reference circuit comprises:

a reference control circuit configured to receive one or more input signals associated with the one or more memory conditions and generate one or more output signals in response thereto;

a variable capacitance reference circuit coupled to the reference control circuit and receiving the one or more output signals thereof, operable to generate a capacitance having a value that is a function of the one or more output signals of the reference control circuit,

wherein the capacitance of the variable capacitance reference circuit couples to one of the bit lines in the bit line pair and forms a capacitive divider therewith, thereby defining the reference voltage.

11. The ferroelectric memory of claim 10, wherein the reference control circuit receives one or more signals indicative of the one or more memory conditions and generates a multi-bit control word that dictates a capacitance value of the variable capacitance reference circuit.

12. The ferroelectric memory of claim 11, wherein the variable capacitance reference circuit comprises a plurality of capacitors coupled together in parallel through a plurality of control switches, respectively, wherein each of the plurality of control switches are connected to one of the bits of the multi-bit control word, and wherein based on a state of the multi-bit control word, a selected one or more of the control switches are activated to coupled their respective capacitors together in parallel to generate a reference capacitance.

13. The ferroelectric memory of claim 12, wherein the plurality of capacitors comprise ferroelectric capacitors.

14. The ferroelectric memory of claim 13, wherein the plurality of ferroelectric capacitors are substantially identical in size as ferroelectric capacitors within the ferroelectric memory cells.

15. The ferroelectric memory of claim 13, wherein each of the plurality of ferroelectric capacitors have differing capacitance values in accordance with a binary weighting thereof.

16. The ferroelectric memory of claim 10, wherein the capacitance of the variable capacitance reference circuit couples to one of the bit lines in each of the plurality of bit lines pairs and forms a shared capacitive divider therewith, thereby defining the reference voltage that serves as a shared reference voltage for each of the bit line pairs.

17. A 1T1C ferroelectric memory device, comprising:

a plurality of bit lines pairs, having ferroelectric memory cells selectively coupled thereto;

a sense amplifier circuit coupled across a bit line pair, and operable to generate an output state indicative of a voltage difference across the bit line pair associated therewith;

a logic programmable capacitance reference circuit operable to generate a reference voltage having a value that is a function of one or more memory conditions, the logic programmable capacitance reference circuit further comprising;

a variable capacitance reference circuit comprising a plurality of ferroelectric capacitors selectively coupled together in parallel via a plurality of control switches, respectively, wherein a state of the control switches is dictated by the one or more memory conditions, thereby defining a capacitance value that is a function of the one or more memory conditions,

wherein the plurality of bit line pairs collectively form a memory block, and wherein the capacitance of the variable capacitance reference circuit couples to one of the bit lines in each of the plurality of bit line pairs, and forms a capacitive divider therewith, thereby defining the reference voltage that serves as a shared reference voltage for each of the bit line pairs.