Content addressable control system
First Claim
1. A content addressable arrayed control system, comprising a plurality of control cells each comprising a plurality of memory cells, each memory cell receiving a respective one of a plurality of data lines distributed to all of said control cells and a respective one of a plurality of timing lines distributed to all of said control cells, and a load line distributed only to one of the control cells of said plurality of control cells, each memory cell comprising:
- a 1-bit latch triggered by said load line to latch a signal on said respective data line; and
a 1-bit comparator comparing an output of said latching circuit with a signal on said respective timing line and outputting a valid bit compare signal on an output line commonly connected to the comparators of all memory cell of said control cell, an address compare signal on said output line being valid only when all of said comparators of said control cell output valid bit compare signals.
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Accused Products
Abstract
Pulse-width modulation (PWM) control and drive circuitry particularly applicable to an array of electrostatic actuators formed in a micro electromechanical system (MEMS), such as used for optical switching. The high-voltage portion may be incorporated in an integrated circuit having drive cells vertically aligned with the MEMS elements. A control cell associated with each actuator includes a register selectively stored with a desired pulse width. A clocked counter distributes its outputs to all control cells. When the counter matches the register, a polarity signal corresponding to a drive clock is latched and controls the voltage applied to the electrostatic cell. The MEMS element may be a tiltable plate supported in its middle by a torsion beam. Complementary binary signals may drive two capacitors formed across the axis of the beam. The register and comparison logic for each cell may be formed by a content addressable memory.
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Citations
9 Claims
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1. A content addressable arrayed control system, comprising a plurality of control cells each comprising a plurality of memory cells, each memory cell receiving a respective one of a plurality of data lines distributed to all of said control cells and a respective one of a plurality of timing lines distributed to all of said control cells, and a load line distributed only to one of the control cells of said plurality of control cells, each memory cell comprising:
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a 1-bit latch triggered by said load line to latch a signal on said respective data line; and
a 1-bit comparator comparing an output of said latching circuit with a signal on said respective timing line and outputting a valid bit compare signal on an output line commonly connected to the comparators of all memory cell of said control cell, an address compare signal on said output line being valid only when all of said comparators of said control cell output valid bit compare signals. - View Dependent Claims (2, 3, 4, 5)
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6. A content addressable control section for controlling N time delays supplied to a plurality N of drive sections, comprising:
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a multi-bit data bus;
N registers seletively connected in parallel to said data bus;
at least one control line connected to said N registers to reset said registers according to data on said data bus; and
a single clocked counter connected to respective ones of said registers and providing an output in comparision to said connected registers. - View Dependent Claims (7, 8, 9)
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Specification