Content addressable control system

• US 20040174757A1
• Filed: 03/12/2004
• Published: 09/09/2004
• Est. Priority Date: 01/26/2001
• Status: Active Grant

• Current Assignee: Lumentum Operations, LLC (Lumentum Holdings Inc.)
• Original Assignee: Michael L. Nagy, Steven L. Garverick
• Inventors: Nagy, Michael L., Garverick, Steven L.
• Granted Patent: US 6,961,257 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G02B 2006/12104 Mirror; Reflectors or the like
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means
• CPC Class Codes: G02B 6/266 the optical element being an attenuator
• CPC Class Codes: G02B 6/3512 the optical element being reflective, e.g. mirror
• CPC Class Codes: G02B 6/3518 the reflective optical element being an intrinsic part of a MEMS device, i.e. fabricated together with the MEMS device MEMS devices in general B81B; manufacture of MEM devices in general B81C; micromechanical devices controlling the direction of light G02B26/0833
• CPC Class Codes: G02B 6/3556 NxM switch, i.e. regular arrays of switches elements of matrix type constellation
• CPC Class Codes: G02B 6/356 in an optical cross-connect device, e.g. routing and switching aspects of interconnecting different paths propagating different wavelengths to (re)configure the various input and output links switching polarized beams G02B6/3594; power equalizers G02B6/356 and G02B6/3594; path selecting means H04Q11/0001
• CPC Class Codes: G02B 6/357 Electrostatic force electrostatic forces controlling reflecting elements in general G02B26/0841
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 2011/0022 using fibre gratings
• CPC Class Codes: H04Q 2011/0024 using space switching
• CPC Class Codes: H04Q 2011/003 using switches based on microelectro-mechanical systems [MEMS]
• CPC Class Codes: H04Q 2011/0039 Electrical control
• CPC Class Codes: H04Q 2011/0049 Crosstalk reduction; Noise; Power budget

Abstract

Pulse-width modulation (PWM) control and drive circuitry particularly applicable to an array of electrostatic actuators formed in a micro electromechanical system (MEMS), such as used for optical switching. The high-voltage portion may be incorporated in an integrated circuit having drive cells vertically aligned with the MEMS elements. A control cell associated with each actuator includes a register selectively stored with a desired pulse width. A clocked counter distributes its outputs to all control cells. When the counter matches the register, a polarity signal corresponding to a drive clock is latched and controls the voltage applied to the electrostatic cell. The MEMS element may be a tiltable plate supported in its middle by a torsion beam. Complementary binary signals may drive two capacitors formed across the axis of the beam. The register and comparison logic for each cell may be formed by a content addressable memory.

Claims

1. A content addressable arrayed control system, comprising a plurality of control cells each comprising a plurality of memory cells, each memory cell receiving a respective one of a plurality of data lines distributed to all of said control cells and a respective one of a plurality of timing lines distributed to all of said control cells, and a load line distributed only to one of the control cells of said plurality of control cells, each memory cell comprising:

a 1-bit latch triggered by said load line to latch a signal on said respective data line; and

a 1-bit comparator comparing an output of said latching circuit with a signal on said respective timing line and outputting a valid bit compare signal on an output line commonly connected to the comparators of all memory cell of said control cell, an address compare signal on said output line being valid only when all of said comparators of said control cell output valid bit compare signals.

2. The system of claim 1, wherein each control cell further includes an output latch latching in response to said output signal a state signal on a state line distributed to all output latches of said said plurality of control cells.

3. The system of claim 2, further comprising a counter driven by a clock signal having a high-order bit driving said state line and lower-order bits driving respective ones of said timing lines.

4. The system of claim 3, further comprising an address decoder receiving a multi-bit address signal and enabling in response thereto only one of said load lines.

5. The system of claim 3, wherein count intervals of said counter are non-uniform in duration.

6. A content addressable control section for controlling N time delays supplied to a plurality N of drive sections, comprising:

a multi-bit data bus;

N registers seletively connected in parallel to said data bus;

at least one control line connected to said N registers to reset said registers according to data on said data bus; and

a single clocked counter connected to respective ones of said registers and providing an output in comparision to said connected registers.

7. The control section of claim 6, wherein said trigger signal is synchronous with a clock signal.

8. The control section of claim 6, wherein said trigger signal is aperiodic.

9. The control section of claim 6, wherein said registers and counters are arranged in rows and columns and wherein seach of registers is controlled by a row enable signal, a column enable signal, and a load signal.