Network switch memory interface configuration
First Claim
1. A network switch for network communications, said network switch comprising:
- a first data port interface, said first data port interface supporting a plurality of data ports for transmitting and receiving data at a first data rate;
a second data port interface, said second data port interface supporting a plurality of data ports for transmitting and receiving data at a second data rate;
a third data port interface for transmitting and receiving data at a third data rate;
a CPU interface, said CPU interface configured to communicate with a CPU;
a first internal memory, said first internal memory communicating with said first data port interface, said second data port interface, and said third data port interface;
a first memory management unit, said first memory management unit including an external memory interface for communicating data from at least one of said first data port interface and said second data port interface to and from an external memory;
a second internal memory, said second internal memory communicating with said third data port interface;
a second memory management unit, said second memory management unit controlling access to and from said second internal memory; and
a communication channel, said communication channel for communicating data and messaging information between said first data port interface, said second data port interface, said third data port interface, said first internal memory, and said first memory management unit, wherein said first memory management unit directs data from one of said first data port, said second data port, and said third data port to one of said internal memory and said external memory interface according to a predetermined algorithm.
6 Assignments
0 Petitions
Accused Products
Abstract
A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first internal memory communicating with the first data port interface, the second data port interface, and the third data port interface. A first memory management unit having an external memory interface for communicating data from at least one of the first data port interfaces and the second data port interface to and from an external memory is also provided. A second internal memory is provided, the second internal memory communicating with the third data port interface. A second memory management unit is provided and used to control access to and from the second internal memory. A communication channel is provided for communicating data and messaging information between the first data port interface, the second data port interface, the third data port interface, the first internal memory, and the first memory management unit. The first memory management unit directs data from one of the first data ports, the second data ports, and the third data ports to one of the internal memory and the external memory interfaces according to a predetermined algorithm.
-
Citations
19 Claims
-
1. A network switch for network communications, said network switch comprising:
-
a first data port interface, said first data port interface supporting a plurality of data ports for transmitting and receiving data at a first data rate;
a second data port interface, said second data port interface supporting a plurality of data ports for transmitting and receiving data at a second data rate;
a third data port interface for transmitting and receiving data at a third data rate;
a CPU interface, said CPU interface configured to communicate with a CPU;
a first internal memory, said first internal memory communicating with said first data port interface, said second data port interface, and said third data port interface;
a first memory management unit, said first memory management unit including an external memory interface for communicating data from at least one of said first data port interface and said second data port interface to and from an external memory;
a second internal memory, said second internal memory communicating with said third data port interface;
a second memory management unit, said second memory management unit controlling access to and from said second internal memory; and
a communication channel, said communication channel for communicating data and messaging information between said first data port interface, said second data port interface, said third data port interface, said first internal memory, and said first memory management unit, wherein said first memory management unit directs data from one of said first data port, said second data port, and said third data port to one of said internal memory and said external memory interface according to a predetermined algorithm. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
Specification