Method for controlling semiconductor processing apparatus

• US 20040175880A1
• Filed: 03/04/2003
• Published: 09/09/2004
• Est. Priority Date: 03/04/2003
• Status: Active Grant

• Current Assignee: Hitachi High-Tech Company Limited (Hitachi, Ltd.)
• Original Assignee: Akira Kagoshima, Hideyuki Yamamoto, Junichi Tanaka, Shoji Ikuhara
• Inventors: Tanaka, Junichi, Ikuhara, Shoji, Yamamoto, Hideyuki, Kagoshima, Akira
• Granted Patent: US 7,010,374 B2
• Time in Patent Office: Days
• US Class Current: 438/209
• CPC Class Codes: H01L 21/67028 for cleaning followed by drying, rinsing, stripping, blasting or the like
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: Y10S 438/905 Cleaning of reaction chamber

Abstract

A method for controlling a semiconductor processing apparatus including a vacuum processing chamber, a plasma apparatus for generating plasma inside the vacuum processing chamber, and a process controller for controlling a process by holding a process recipe including plasma cleaning of inside of the vacuum processing chamber constant, comprises the steps of detecting process abnormality of the process on the basis of sensor data detected by sensors arranged in the semiconductor processing apparatus, and executing a recovery step for removing deposition deposited inside the vacuum processing chamber when abnormality is detected.

Claims

1. A method for controlling a semiconductor processing apparatus including a vacuum processing chamber, a plasma generation apparatus for generating plasma inside said vacuum processing chamber, and a process controller for controlling a process by holding a process recipe including plasma cleaning of inside of said vacuum processing chamber constant, comprising the steps of:

detecting process abnormality of said process on the basis of sensor data detected by sensors arranged in said semiconductor processing apparatus; and

executing a recovery step for removing deposition deposited inside said vacuum processing chamber when abnormality of said process is detected.

2. A method for controlling a semiconductor processing apparatus as defined in claim 1, wherein, when any abnormality is detected in said process after processing of a specific sample, said recovery step is executed after processing of a lot containing said sample is completed.

3. A method for controlling a semiconductor processing apparatus as defined in claim 1, wherein heating means is provided to a lower wall portion of said vacuum processing chamber.

4. A method for controlling a semiconductor processing apparatus as defined in claim 1, wherein a plasma generation electrode is provided to a lower wall portion of said vacuum processing chamber.

5. A method for controlling a semiconductor processing apparatus as defined in claim 1, wherein an electrode for supplying a bias potential is provided to a lower wall portion of said vacuum processing chamber.

6. A method for controlling a semiconductor processing apparatus including a vacuum processing chamber, a plasma generation apparatus for generating plasma inside said vacuum processing chamber, and a process controller for controlling a process by holding a process recipe including plasma cleaning of inside of said vacuum processing chamber constant, comprising the steps of:

detecting abnormality of said process on the basis of a principal component score generated by compressing sensor data inclusive of light emission spectral characteristics of said plasma detected by a plurality of sensors arranged in said semiconductor processing apparatus by principal component analysis; and

executing a recovery step for removing deposition deposited inside said vacuum processing chamber when abnormality of said process is detected.

7. A method for controlling a semiconductor processing apparatus as defined in claim 6, wherein, when any abnormality is detected in said process after processing of a specific sample, said recovery step is executed after processing of a lot containing said sample is completed.

8. A method for controlling a semiconductor processing apparatus as defined in claim 6, wherein heating means is provided to a lower wall portion of said vacuum processing chamber.

9. A method for controlling a semiconductor processing apparatus as defined in claim 6, wherein a plasma generation electrode is provided to a lower wall portion of said vacuum processing chamber.

10. A method for controlling a semiconductor processing apparatus as defined in claim 6, wherein an electrode for supplying a bias potential is provided to a lower wall portion of said vacuum processing chamber.

11. A method for controlling a semiconductor processing apparatus including a vacuum processing chamber, a plasma generation apparatus for generating plasma inside said vacuum processing chamber, and a process controller for controlling a process by holding a process recipe including plasma cleaning of inside of said vacuum processing chamber constant, comprising the steps of:

executing trend anticipation as to whether or not process abnormality develops in next sample processing on the basis of sensor data inclusive of light emission spectral characteristics of said plasma detected by a plurality of sensors arranged in said semiconductor processing apparatus; and

executing a recovery step for removing deposition deposited inside said vacuum processing chamber when occurrence of said process abnormality is determined.

12. A method for controlling a semiconductor processing apparatus as defined in claim 11, wherein, when any abnormality is detected in said process after processing of a specific sample, said recovery step is executed after processing of a lot containing said sample is completed.

13. A method for controlling a semiconductor processing apparatus as defined in claim 11, wherein heating means is provided to a lower wall portion of said vacuum processing chamber.

14. A method for controlling a semiconductor processing apparatus as defined in claim 11, wherein a plasma generation electrode is provided to a lower wall portion of said vacuum processing chamber.

15. A method for controlling a semiconductor processing apparatus as defined in claim 11, wherein an electrode for supplying a bias potential is provided to a lower wall portion of said vacuum processing chamber.