Apparatus and method for testing electronic systems

• US 20040176924A1
• Filed: 05/29/2003
• Published: 09/09/2004
• Est. Priority Date: 03/07/2003
• Status: Active Grant

• Current Assignee: Salmon Technologies LLC
• Original Assignee: Salmon Technologies LLC
• Inventors: Salmon, Peter C.
• Granted Patent: US 7,505,862 B2
• Time in Patent Office: Days
• US Class Current: 702/125
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

The technology and economics of system testing have evolved to the point where a radical change in methodology is needed for effective functional testing of systems at clock rates of 1 GHz and higher. Rather than providing a test fixture to interface between the system under test and an external tester, it is preferable to provide critical testing functions within each electronic system in the form of one or more special-purpose test chips. An architecture is proposed that supports full-speed testing with improved noise margins, and also efficient methods for learning correct system behavior and generating the test vectors. The test program is preferably written using the same programming language as used for the system application.

Claims

1. A method for testing electronic system behavior comprising the steps of:

providing a test chip that resides in said system;

providing a timing reference signal to said test chip;

operating said system using a test program;

capturing signals of interest of said system during operation using sampling circuits provided on said test chip; and

functionally testing said system by comparing in said test chip said captured signals with signals representing known good system behavior.

2. The method of claim 1 wherein said signals representing known good system behavior are test vectors.

3. The method of claim 2 wherein said test vectors are predetermined and stored on said test chip.

4. The method of claim 1 wherein said signals representing known good system behavior are provided by a second system operating in parallel with the system under test.

5. The method of claim 1, including the generation of one or more test strobes from said timing reference signal, said test strobes being used to control the timing of said sampling circuits and said comparator circuits.

6. The method of claim 1 and including provision of a test mask that provides a means to select critical test cycles as a subset of all system cycles.

7. The method of claim 3 wherein said predetermined test vectors are learned by capturing and storing behavior of a correctly functioning system.

8. The method of claim 1 wherein said test program is written in the same programming language as the system application software.

9. An apparatus of an electronic system comprising:

a test support computer connected to said electronic system;

one or more test chips embedded in said electronic system that communicate with said test support computer using selected ones of said connections;

said test chips including sampling circuits, comparator circuits and memory circuits for capturing signals of interest of said electronic system, comparing said signals of interest against predetermined test signals, and storing the results of said comparisons, respectively.

10. The apparatus of claim 9 and further including a test mask for controlling when to sample and test said signals of interest.

11. The apparatus of claim 9 wherein said sampling circuits are capable of capturing digital signals.

12. The apparatus of claim 9 wherein said sampling circuits are capable of capturing analog signals.

13. The apparatus of claim 9 wherein said sampling circuits are capable of capturing radio frequency signals.

14. An integrated circuit test chip comprising:

sampling circuits for sampling behavior of a system under test;

comparator circuits for comparing said sampled behavior with known good behavior; and

a mask memory for controlling when to sample said behavior of said system under test.

15. The integrated circuit test chip of claim 14 wherein said sampling circuits are capable of capturing digital signals.

16. The integrated circuit test chip of claim 14 wherein said sampling circuits are capable of capturing analog signals.

17. The integrated circuit test chip of claim 14 wherein said sampling circuits are capable of capturing radio frequency signals.

18. A method of learning system behavior for test purposes comprising the steps of:

providing a functionally correct system;

generating a test program that exercises all of the important functions and components of said functionally correct system;

augmenting said test program with special test instructions that highlight particular system cycles that represent critical system behavior; and

,

capturing said highlighted critical system behavior in the form of test vectors.

19. The method of claim 18 and including refinement of said test vectors to find a minimum set that represents all of the critical behaviors of said functionally correct system.

20. An apparatus for testing electronic system behavior comprising:

a test support computer;

one or more test chips embedded in said electronic system that communicate with said test support computer;

said test chips including

sampling circuits for capturing system behavior signals at selected times;

reference memory circuits for storing signals representing good system behavior at said selected times;

comparator circuits for comparing said captured system behavior signals with said good system behavior signals at said selected times, and

fail memory means for storing failed comparisons.

21. An apparatus as in claim 20 including a mask memory for storing and selecting test periods.