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Block synchronous decoding

  • US 20040176956A1
  • Filed: 03/04/2003
  • Published: 09/09/2004
  • Est. Priority Date: 03/04/2003
  • Status: Active Grant
First Claim
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1. A continuous pattern recognition system comprising:

  • an input device adapted to provide a digital representation of an input;

    memory operably coupled to the input device to store the digital representation and a plurality of multi-state models relative to the digital representation;

    a processor coupled to the input device, and the memory, the processor including a cache memory, and adapted to convert the digital representation into a plurality of time-sequenced frames; and

    wherein the processor is adapted to generate an output of recognized patterns based upon processing the time-sequenced frames and blocks of the multi-state models stored in the cache memory.

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