Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller

• US 20040177126A1
• Filed: 02/18/2003
• Published: 09/09/2004
• Est. Priority Date: 02/18/2003
• Status: Active Grant

• Current Assignee: Dot Hill Systems Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Chaparral Network Storage, Inc. (Seagate Technology Holdings Plc)
• Inventors: Maine, Gene
• Granted Patent: US 7,143,227 B2
• Time in Patent Office: Days
• US Class Current: 709/217
• CPC Class Codes: G06F 11/2087 with a common controller
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.

Claims

1. A broadcast bridge apparatus, comprising:

a first port, for receiving data transmitted on a first local bus;

a second port, coupled to said first port, for receiving said data from said first port and providing said data for retransmission on a second local bus to a first memory subsystem; and

a third port, coupled to said first port, for receiving a copy of said data from said first port and selectively providing said copy of said data for retransmission on a third local bus to a second memory subsystem.

2. The apparatus of claim 1, wherein said third port selectively provides said copy of said data for retransmission on said third local bus to said second memory subsystem substantially concurrently with said first port providing said data for retransmission on said second local bus to said first memory subsystem.

3. The apparatus of claim 1, wherein said first and second memory subsystems are redundant.

4. The apparatus of claim 1, wherein said data originates from a host computer and is destined to be written from one of said first and second memory subsystems to one or more storage devices.

5. The apparatus of claim 1, wherein said first memory subsystem is alleviated from copying said data to said second memory subsystem due to said third port providing said copy of said data.

6. The apparatus of claim 1, wherein said first port is configured to receive an address of said data from said first local bus, wherein said third port selectively provides said copy of said data to said second memory subsystem only if said address lies within one or more address ranges of said first local bus, wherein said one or more address ranges comprise a subset of an address space of said first local bus.

7. The apparatus of claim 6, wherein said one or more address ranges are predetermined.

8. The apparatus of claim 6, wherein said one or more address ranges are programmable.

9. The apparatus of claim 6, further comprising:

a programmable control register, coupled to said third port, for storing a control value, wherein said third port selectively provides said copy of said data to said second memory subsystem only if said control value specifies said providing said copy of said data to said second memory subsystem and said address lies within said address range.

10. The apparatus of claim 1, further comprising:

a control register, coupled to said third port, for storing a control value, wherein said third port selectively provides said copy of said data to said second memory subsystem only if said control value specifies said providing said copy of said data to said second memory subsystem.

11. The apparatus of claim 10, wherein said control register is programmable.

12. The apparatus of claim 1, further comprising:

a first-in-first-out (FIFO) memory, coupling said first port to said third port, for selectively buffering said copy of said data.

13. The apparatus of claim 12, further comprising:

a second FIFO memory, coupling said first port to said second port, for buffering said data.

14. The apparatus of claim 1, further comprising:

communication logic, coupling said second port to said third port, whereby said first memory subsystem informs said second memory subsystem of said retransmission of said copy of said data to said second memory subsystem.

15. The apparatus of claim 1, wherein at least one of said first, second, and third local buses comprise a PCI-X (Peripheral Component Interconnect-X) bus.

16. The apparatus of claim 1, wherein at least one of said first, second, and third local buses comprise a Peripheral Component Interconnect (PCI) bus.

17. A bus bridge apparatus for broadcasting data from a first local bus on one side of the bridge to a plurality of redundant storage controllers coupled to second and third local buses on an opposite side of the bridge to relieve the redundant controllers from copying the data to one another, the apparatus comprising:

a first FIFO memory, coupled to receive data from the first local bus, said data associated with a first write transaction on the first local bus;

first master logic, coupled to said first FIFO memory, for causing a second write transaction on the second local bus to transfer said data from said first FIFO memory to a first of the plurality of redundant storage controllers;

a second FIFO memory, coupled to receive said data from the first local bus; and

second master logic, coupled to said second FIFO memory, for causing a third write transaction on the third local bus to transfer said data from said second FIFO memory to a second of the plurality of redundant storage controllers.

18. The apparatus of claim 17, further comprising:

target logic, coupled to said first and second master logic, for receiving a write command of said first write transaction on the first local bus, and for generating first and second signals to said first and second master logic, respectively, to signify a transfer of said data into said first and second FIFO memories, respectively, in response to said first write transaction.

19. The apparatus of claim 18, wherein said first and second master logic generate third and fourth signals, respectively, to signify to said target logic completion of said second and third write transactions, respectively.

20. The apparatus of claim 17, wherein said transfer of said data from said second FIFO memory to said second of the plurality of redundant storage controllers occurs substantially simultaneously with said transfer of said data from said first FIFO memory to said first of the plurality of redundant storage controllers.

21. The apparatus of claim 17, wherein said first and second master logic comprise PCI-X master logic.

22. A PCI-X bus bridge, for bridging a first PCI-X bus to second and third PCI-X buses, comprising:

first, second, and third PCI-X interfaces, coupled to the first, second, and third PCI-X buses, respectively, said first PCI-X interface configured to receive a plurality of write transactions from the first PCI-X bus; and

a plurality of broadcast bridge circuits, coupling said first PCI-X interface to said second and third PCI-X interfaces, each for causing both of said second and third PCI-X interfaces to retransmit a respective one of said plurality of write transactions on the second and third PCI-X buses, respectively.

23. The apparatus of claim 22, further comprising:

first, second, and third multiplexing logic, coupled to said first, second, and third PCI-X interfaces, respectively, for selectively coupling said first, second, and third PCI-X interfaces, respectively, to one of said plurality of broadcast bridge circuits.

24. The apparatus of claim 23, wherein each of said plurality of broadcast bridge circuits includes a busy output for indicating whether said broadcast bridge circuit is currently servicing a PCI-X command.

25. The apparatus of claim 24, wherein said first, second, and third multiplexing logic selectively couples said first, second, and third PCI-X interfaces, respectively, to one of said plurality of broadcast bridge circuits based on said busy outputs.

26. A PCI-X bus bridge, comprising:

a PCI-X target circuit, for receiving a PCI-X write command from a first PCI-X bus coupled to one side of the bus bridge, said PCI-X write command specifying an address of data to be written;

a control input to said PCI-X target circuit, for indicating whether said address is within an address range of an address space of said first PCI-X bus;

a write FIFO, coupled to said PCI-X target circuit, for receiving said data from said first PCI-X bus for retransmission on a second PCI-X bus coupled to a side of the bus bridge opposite said first PCI-X bus; and

a broadcast FIFO, coupled to said PCI-X target circuit, for receiving a copy of said data from said first PCI-X bus for retransmission on a third PCI-X bus coupled to said opposite side of the bus bridge, wherein said broadcast FIFO receives said copy of said data only if said address is within said address range.

27. The PCI-X bus bridge of claim 26, further comprising:

a first PCI-X master circuit, coupled to said PCI-X target circuit, for retransmitting said data on said second PCI-X bus from said write FIFO; and

a second PCI-X master circuit, coupled to said PCI-X target circuit, for retransmitting said copy of said data on said third PCI-X bus from said broadcast FIFO only if said address is within said address range.

28. The PCI-X bus bridge of claim 27, wherein said second PCI-X master circuit retransmits said copy of said data on said third PCI-X bus from said broadcast FIFO substantially simultaneously with said first PCI-X master circuit retransmitting said data on said second PCI-X bus from said write FIFO.

29. A method for selectively performing a broadcast data transfer across a bus bridge to a plurality of redundant memory subsystems in a storage controller, comprising:

receiving data on a first bus on one side of the bus bridge;

writing said data to a first of the plurality of memory subsystems on a second bus on an opposite side of the bus bridge from said first bus;

determining whether the bus bridge is enabled to perform broadcast data transfers; and

writing a copy of said data to a second of the plurality of memory subsystems on a third bus on said opposite side of the bus bridge only if the bus bridge is enabled to perform broadcast data transfers, wherein the bus bridge writes said copy of said data to said second of the plurality of memory subsystems on said third bus substantially concurrently with said writing said data to said first of the plurality of memory subsystems on said second bus.

30. The method of claim 29, further comprising:

receiving an address of said data on said first bus; and

determining whether said address is within an address range, said address range being a subset of an address space of said first bus;

wherein said writing said copy of said data to said second of the plurality of memory subsystems is performed only if said address is within said address range.

31. The method of claim 29, further comprising:

storing said data into a first buffer in response to said receiving said data on said first bus and prior to said writing said data to said first of the plurality of memory subsystems;

storing said copy of said data into a second buffer concurrently with said storing said data into said first buffer only if the bus bridge is enabled to perform broadcast data transfers.

32. The method of claim 31, further comprising:

reading said data from said first buffer to provide said data for said writing said data to said first of the plurality of memory subsystems; and

reading said copy of said data from said second buffer to provide said copy of said data for said writing said copy of said data to said second of the plurality of memory subsystems.

33. The method of claim 29, wherein said first, second, and third buses comprise PCI-X buses.

34. A redundant network storage controller, comprising:

at least one I/O interface circuit, for receiving data from a host computer and writing said data to one or more storage devices;

a primary memory subsystem, for buffering said data before being written to said storage devices;

a secondary memory subsystem, for storing a redundant copy of said data; and

a plurality of bus bridges, for bridging a bus coupled to said at least one I/o interface circuit with a plurality of buses coupled to said primary and secondary memory subsystems, configured to write said data received on said bus concurrently to said primary and secondary memory subsystems on first and second of said plurality of buses, respectively.

35. The controller of claim 34, wherein each of said plurality of bus bridges comprises:

a first port for coupling to said bus coupled to said at least one I/O interface circuit;

a second port for coupling to said first of said plurality of buses coupled to said primary memory subsystem; and

a third port for coupling to said second of said plurality of buses coupled to said secondary memory subsystem.

36. The controller of claim 35, wherein each of said plurality of bus bridges further comprises:

a first buffer, coupling said first and second ports, for buffering said data between said bus and said first of said plurality of buses; and

a second buffer, coupling said first and third ports, for buffering said data between said bus and said second of said plurality of buses.

37. The controller of claim 34, wherein said primary memory subsystem updates said secondary memory subsystem with information specifying a presence of said data in said secondary subsystem after said data is written to said secondary memory subsystem.