Semiconductor apparatus

• US 20040177256A1
• Filed: 01/09/2004
• Published: 09/09/2004
• Est. Priority Date: 01/09/2003
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kobayashi, Shinichiro
• Application Number:
  US10/755,120
• Publication Number:
  US 20040177256A1
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00

Abstract

A semiconductor apparatus is provided that includes memories for storing an externally input key or data at a received address, key comparison sections for comparing the externally input key with keys output from the memories, a first-hash-function calculation section for associating the externally input key with a first address in many-to-one correspondence, a second-hash-function calculation section for associating the first address with a second address in one-to-one correspondence, a data writing processing section for sending the first or second address to the memories to store data, and a data reading processing section for sending the first or second address to the memories to read data.

Claims

1. A semiconductor apparatus for storing a key and data, comprising:

first to N-th (N is a natural number equal to or greater than two) storage sections having first to N-th storage capacities, respectively, the storage sections;

storing an externally-input key or data at a received address in key-and data writing; and

when a key and data are stored at a received address, outputting the key and data; and

when a key or data is not stored at a received address, outputting a first signal indicating that a key or data is not stored at the received address, in key-and-data reading;

first to N-th comparison sections, the comparison sections;

comparing the externally input key with keys output from the first to N-th storage sections; and

when the externally input key matches the keys output from the first to N-th storage sections, outputting a second signal indicating that the externally input key matches the keys output from the first to N-th storage sections; and

when the first to N-th storage sections output the first signals, outputting a third signal indicating that the first to N-th storage sections output the first signals, in key-and-data writing into the first to N-th storage sections; and

comparing the externally input key with keys output from the first to N-th storage sections; and

when the externally input key matches the keys output from the first to N-th storage sections, externally outputting data output from a storage section which outputs the key that matches the externally input key, among the first to N-th storage sections, in key-and-data reading from the first to N-th storage sections;

a first calculation section performing a first calculation which associates the externally input key with a first address in many-to-one correspondence;

a second calculation section performing a second calculation which associates the first address with a second address in one-to-one correspondence;

a first processing section operating when a key and data are written, the first processing section;

sending the first address to the first to N-th storage sections; and

when the second signal is received from the M-th (M is a natural number equal to or less than N) comparison section, storing the externally input data at the first address in the M-th storage section;

when the second signal is not received from any of the first to N-th comparison sections and the third signal is received from one or more of the first to N-th comparison sections, storing the externally input key and data at the first address in the first storage section obtained when a storage section or storage sections that output the first signal among the first to N-th storage sections are arranged in a first order;

when the second signal is not received from any of the first to N-th comparison sections and the third signal is not received from any of the first to N-th comparison sections, sending the second address to the first to N-th storage sections;

when the second signal is received from the L-th (L is a natural number equal to or less than N) comparison section, storing the externally input data at the second address in the L-th storage section; and

when the second signal is not received from any of the first to N-th comparison sections and the third signal is received from one or more of the first to N-th comparison sections, storing the externally input key and data at the second address in the first storage section obtained when a storage section or storage sections that output the first signal among the first to N-th storage sections are arranged in a second order; and

a second processing section operating when data is read, the second processing section;

sending the first address to the first to N-th storage sections; and

when the second signal is not received from any of the first to N-th comparison sections, sending the second address to the first to N-th storage sections.