Double-buffering of pixel data using copy-on-write semantics

• US 20040179019A1
• Filed: 03/12/2003
• Published: 09/16/2004
• Est. Priority Date: 03/12/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sabella, Paolo E., Wilt, Nicholas P.
• Granted Patent: US 6,911,983 B2
• Time in Patent Office: Days
• US Class Current: 345/537
• CPC Class Codes: G06F 3/1415 with means for detecting differences between the image stored in the host and the images displayed on the displays
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2350/00 Solving problems of bandwidth in display systems
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

Tile buffers in a graphics processing system are managed use “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. Two memory spaces store tile data, and two logical buffers are used to access the memory spaces. For each tile, a tile association is maintained, indicating which of the two memory spaces is associated with each of the two logical buffers. To copy a tile of the first logical buffer to the second logical buffer, the tile association for the tile being copied is modified. Data for a tile is written to the memory space associated with a target logical buffer after ensuring that the tile association for the tile associates the target logical buffer with a different one of the two memory spaces from the other logical buffer.

Claims

1. A buffer system for storing tile data for a plurality of tiles of a display, comprising:

a first memory space for storing tile data;

a second memory space for storing tile data;

a memory interface circuit configured to receive memory access commands referencing a first logical buffer and a second logical buffer, the memory interface circuit further configured to respond to the memory access commands by accessing the first and second memory spaces; and

a tile table configured to store an entry for each of a plurality of tiles, each entry associating each of the first logical buffer and the second logical buffer with one of the first and second memory spaces,

wherein the memory interface circuit uses the tile table entries to determine and modify associations of tiles of the first and second logical buffers with the first and second memory spaces.

2. The buffer system of claim 1 wherein the memory interface circuit is further configured to respond to a command to read data for a tile of the first logical buffer by identifying from the tile table entry for the tile which of the first and second memory spaces is associated with the first logical buffer and accessing the identified memory space.

3. The buffer system of claim 1 wherein the memory interface circuit is further configured to respond to a command to copy a tile of the first logical buffer to the second logical buffer by modifying the tile table entry for the tile to associate the second logical buffer with the one of the first and second memory spaces associated with the first logical buffer, without accessing either of the first and second memory spaces.

4. The buffer system of claim 1 wherein the memory interface circuit is further configured to respond to a command to write data to a tile of the first logical buffer by modifying the tile table entry for the tile to associate the first and second logical buffers with different ones of the first and second memory spaces prior to writing the tile data to the one of the first and second memory spaces associated with the first logical buffer.

5. The buffer system of claim 1 wherein the memory interface circuit is implemented on a chip and the tile table includes a register array implemented on the chip.

6. The buffer system of claim 1 wherein each tile table entry includes a four-valued state indicator.

7. The buffer system of claim 6 wherein the state indicator includes:

a first bit indicating which of the first and second memory spaces is associated with the first logical buffer; and

a second bit indicating which of the first and second memory spaces is associated with the second logical buffer.

8. The buffer system of claim 6 wherein the state indicator includes:

a first bit indicating which of the first and second memory spaces is associated with the first logical buffer; and

a second bit indicating whether the second logical buffer is associated with the same one of the first and second memory spaces as the first buffer.

9. The buffer system of claim 1 wherein the first memory space and the second memory space are located in one or more random access memory (RAM) arrays.

10. A method for managing graphics data for a plurality of tiles of a display, the method comprising:

establishing a tile association for each of the plurality of tiles, each tile association indicating which of two memory spaces for storing tile data for that tile is associated with each of a first logical buffer and a second logical buffer, wherein the two memory spaces are accessible by referencing the first logical buffer and the second logical buffer;

copying a tile of the first logical buffer to the second logical buffer by modifying the tile association for the tile; and

writing updated tile data for a tile of the second logical buffer to the one of the two memory spaces associated with the second logical buffer after updating the tile association for the tile so that the first and second logical buffers are associated with different ones of the two memory spaces.

11. The method of claim 10 wherein the act of writing updated tile data for a tile of the second logical buffer includes:

reading tile data for the tile from the memory space associated with the second logical buffer;

updating the tile data;

determining from the tile association for the tile whether the first logical buffer and the second logical buffer are both associated with a same one of the two memory spaces;

in response to determining that the first logical buffer and the second logical buffer are both associated with the same one of the two memory spaces, modifying the tile association for the tile to indicate that the second logical buffer is associated with the other one of the two memory spaces; and

writing the updated data for the tile to the one of the two memory spaces associated with the second logical buffer.

12. The method of claim 10 wherein the act of copying a tile of the first logical buffer to the second logical buffer is performed for each of the plurality of tiles upon reaching the end of a scanout operation on the second logical buffer.

13. The method of claim 10 wherein the act of writing updated tile data for a tile is performed in response to a command received from an application executing on a central processing unit.

14. The method of claim 10 wherein the act of writing updated tile data for a tile is performed in response to a command received from a graphics processor.

15. The method of claim 10 wherein the act of establishing a tile association includes providing a tile table having an entry for each of the plurality of tiles.

16. The method of claim 15 wherein each tile table entry includes a four-valued state indicator.

17. The method of claim 16 wherein each state indicator includes:

a first bit indicating which of the two memory spaces is associated with the first logical buffer; and

a second bit indicating which of the two memory spaces is associated with the second logical buffer.

18. The method of claim 16 wherein the state indicator includes:

a first bit indicating which of the two memory spaces is associated with the first logical buffer; and

a second bit indicating whether the second logical buffer is associated with the same one of the two memory spaces as the first buffer.

19. A method for managing graphics data for a plurality of tiles of a display, the method comprising:

establishing a tile association for each of the plurality of tiles, each tile association indicating which of two memory spaces for storing tile data for that tile is associated with each of a first logical buffer and a second logical buffer, wherein the two memory spaces are accessible by referencing the first logical buffer and the second logical buffer;

scanning out data for each tile of a first display image from the one of the two memory spaces associated with the first logical buffer;

in parallel with the act of scanning out data, writing updated tile data for a tile of a second display image to the one of the two memory spaces associated with the second logical buffer after updating the tile association for the tile so that the first and second logical buffers are associated with different ones of the two memory spaces; and

upon completion of the act of scanning out data, copying each tile of the second logical buffer to the first logical buffer by updating the tile associations.

20. The method of claim 19 further comprising:

after copying the second logical buffer to the first logical buffer, scanning out data for each tile of the second display image from the one of the two memory spaces associated with the second logical buffer; and

in parallel with the second act of scanning out data, writing updated tile data for a tile of a third display image to the one of the two memory spaces associated with the first logical buffer after updating the tile association for the tile so that the first and second logical buffers are associated with different ones of the two memory spaces.

21. The method of claim 19 wherein the act of writing updated tile data for a tile of a second display image includes:

reading tile data for the tile from the memory space associated with the second logical buffer;

updating the tile data for the tile;

determining from the tile association for the tile whether the first logical buffer and the second logical buffer are both associated with a same one of the two memory spaces;

in response to determining that the first logical buffer and the second logical buffer are both associated with the same one of the two memory spaces, modifying the tile association for the tile to indicate that the second logical buffer is associated with the other one of the two memory spaces; and

writing the updated data for the tile to the one of the two memory spaces associated with the second logical buffer.

22. The method of claim 19 wherein the act of writing updated tile data is performed in response to a command received from an application executing on a central processing unit.

23. The method of claim 19 wherein the act of writing updated tile data is performed in response to a command received from a graphics processor.

24. The method of claim 19 wherein the act of writing updated tile data is performed in response to a command received from a desktop compositor.

25. The method of claim 19 wherein the act of establishing a tile association includes providing a tile table having an entry for each of the plurality of tiles.

26. The method of claim 25 wherein each tile table entry includes:

a first bit indicating which of the two memory spaces is associated with the first logical buffer; and

a second bit indicating which of the two memory spaces is associated with the second logical buffer.

27. The method of claim 25 wherein each tile table entry includes:

a first bit indicating which of the two memory spaces is associated with the first logical buffer; and

a second bit indicating whether the second logical buffer is associated with the same one of the two memory spaces as the first buffer.

28. A memory system for managing data for a plurality of tiles, comprising:

a plurality of drawing memories, each configured to receive source tile data for a plurality of tiles from a data source and to store the source tile data in one of a first and a second drawing buffer;

a desktop compositor module configured to read source tile data by accessing selected first drawing buffers of the drawing memories and to generate desktop tile data from the source tile data; and

a desktop frame memory subsystem configured to store desktop tile data received from the desktop compositor module, the desktop frame memory subsystem including;

a first memory space for storing tile data;

a second memory space for storing tile data;

a memory interface circuit configured to receive memory access commands referencing a first desktop buffer and a second desktop buffer, the memory interface circuit further configured to respond to the memory access commands by accessing the first and second memory spaces; and

a tile table configured to store an entry for each of a plurality of tiles, each entry associating each of the first desktop buffer and the second desktop buffer with one of the first and second memory spaces,

wherein the memory interface circuit uses the tile table entries to determine and modify associations of tiles of the first and second desktop buffers with the first and second memory spaces.

29. The memory system of claim 28 wherein the memory interface circuit of the desktop frame memory subsystem is implemented on a chip and the tile table includes a register array located on the chip.

30. The memory system of claim 28 wherein the first and second memory spaces of the desktop frame memory subsystem are located in a graphics memory device.

31. The memory system of claim 28, further comprising:

scanout control logic configured to read tile data from the desktop frame memory subsystem by referencing one of the first and second desktop buffers and to generate display control signals in response to the tile data.

32. The memory system of claim 28 wherein the desktop compositor module is further configured to generate desktop tile data by selecting a tile of one of the first drawing buffers as a tile data source.

33. The memory system of claim 28 wherein the desktop compositor module is further configured to generate desktop tile data by combining tile data from respective first drawing buffers of at least two of the drawing memories.