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CIRCUIT TECHNIQUE FOR COLUMN REDUNDANCY FUSE LATCHES

  • US 20040179412A1
  • Filed: 03/13/2003
  • Published: 09/16/2004
  • Est. Priority Date: 03/13/2003
  • Status: Active Grant
First Claim
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1. A method of delivering address information representing failed elements in an array portion of a device;

  • said method comprising;

    storing respective fail address bit values in a plurality of fuses;

    receiving a signal associated with a respective value of a portion of a further address;

    delivering, when said signal is received, one of said fail address bit values from one of said plurality of fuses to a corresponding latch circuit, said latch circuit receiving fail address bit values from at least two of said plurality of fuses, said one of said fail address bit values being selected based on said value associated with said signal; and

    activating said latch circuit to deliver said fail address bit value.

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