CIRCUIT TECHNIQUE FOR COLUMN REDUNDANCY FUSE LATCHES

• US 20040179412A1
• Filed: 03/13/2003
• Published: 09/16/2004
• Est. Priority Date: 03/13/2003
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Lehmann, Gunther, Frankowsky, Gerd
• Granted Patent: US 6,809,972 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses

Abstract

Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.

Claims

1. A method of delivering address information representing failed elements in an array portion of a device;

said method comprising;

storing respective fail address bit values in a plurality of fuses;

receiving a signal associated with a respective value of a portion of a further address;

delivering, when said signal is received, one of said fail address bit values from one of said plurality of fuses to a corresponding latch circuit, said latch circuit receiving fail address bit values from at least two of said plurality of fuses, said one of said fail address bit values being selected based on said value associated with said signal; and

activating said latch circuit to deliver said fail address bit value.

2. The method of claim 1 wherein said storing step stores fail address bit values representing at least two fail addresses.

3. The method of claim 1 wherein said storing step stores fail address bit values representing at least a portion of a column address.

4. The method of claim 1 wherein said further address is a row address.

5. The method of claim 1 wherein said signal is associated with one of four respective values of a two-bit long portion of said further address.

6. The method of claim 1 wherein said latch circuit receives fail address bit values representing one of at least two fail addresses.

7. The method of claim 1 wherein said signal is received when said further address is received by said device.

8. The method of claim 1 wherein said delivering step delivers at least two of said fail address bit values from at least two of said plurality of fuses to at least two corresponding latch circuits.

9. The method of claim 1 wherein said activating step activates said latch circuit upon receipt of a further signal.

10. A method of delivering address information representing failed elements in an array portion of a device;

said method comprising;

storing respective fail address bit values in a plurality of fuses, said fail address bit values representing up to four column addresses;

receiving, when a row address is received by said device, a signal associated with a respective value of a portion of said row address, said signal being associated with one of four respective values of a two-bit long portion of said row address;

delivering, when said signal is received, one of said fail address bit values from one of said plurality of fuses to a corresponding latch circuit, said latch circuit receiving fail address bit values from four of said plurality of fuses, said one of said fail address bit values being selected based on said value associated with said signal; and

activating, upon receipt of a further signal, said latch circuit to deliver said fail address bit value.

11. A circuit for delivering address information representing failed elements in an array portion of a device;

said circuit comprising;

a plurality of fuses each operative to store a respective fail address bit value;

a plurality of signal lines each associated with a respective value of a portion of a further address;

a plurality of switches each having an input terminal coupled to a corresponding one of said plurality of fuses, a control terminal coupled to an associated one of said plurality of signal lines, and an output terminal; and

at least one latch circuit having a first input coupled to said output of at least two of said plurality of switches and a second input coupled to a pre-charge line, such that when a signal is delivered over a respective one of said plurality of signal lines to said control terminal of said associated one of said plurality of switches, one of said plurality of fail address bit values is delivered from one of said at least two fuses to said first input of said latch circuit, and when a pre-charge signal is then delivered over said pre-charge line to said second input of said latch circuit, said fail address bit value is outputted by said latch circuit.

12. The circuit of claim 11 wherein said plurality of fuses store fail address bit values representing at least two fail addresses.

13. The circuit of claim 11 wherein said respective fail address bit value is a portion of a column address.

14. The circuit of claim 11 wherein said further address is a row address.

15. The circuit of claim 11 wherein said plurality of signal lines comprises four signal lines each representing a respective value of a two-bit long portion of said further address.

16. The circuit of claim 11 wherein said plurality of switches comprises a transistor and said control terminal comprises a gate terminal.

17. The circuit of claim 11 wherein said first input of said latch circuit receives fail address bit values representing one of at least two fail addresses.

18. The circuit of claim 11 wherein said first input of said latch circuit is coupled to up to four of said plurality of switches.

19. The circuit of claim 11 wherein said signal is delivered over said respective one of said plurality of signal lines when said further address is received by said device.

20. A circuit for delivering address information representing failed elements in an array portion of a device;

said circuit comprising;

a plurality of fuses each operative to store a respective fail address bit value, said plurality of fuses store fail address bit values representing at least up to four column addresses;

four signal lines each representing a respective value of a two-bit long portion of a row address;

a plurality of transistor switches each having an input terminal coupled to a corresponding one of said plurality of fuses, a gate terminal coupled to an associated one of said plurality of signal lines, and an output terminal; and

a plurality of latch circuits each having a first input coupled to said output of up to a corresponding four of said plurality of switches and a second input coupled to a pre-charge line, such that when a signal is delivered over a respective one of said plurality of signal lines to each gate terminal of associated ones of said plurality of switches, a respective one of said plurality of fail address bit values is delivered to said first input of each of said plurality of latch circuits from one of its corresponding fuses, and when a pre-charge signal is then delivered over said pre-charge line to each second input of said plurality of latch circuits, each of said plurality of latch circuits delivers its respective fail address bit value.

21. A memory circuit comprising:

a memory array;

a control circuit operable to receive at least one row address value and at least one column address value;

a word line controller operable to receive said row address value from said control circuit and to activate a row of said memory array corresponding to said row address value;

a bit line controller operable to receive said column address value from said control circuit;

a generator circuit operable to receive said row address value address value from said control circuit and to generate a further value based on a portion of said row address value; and

a fuse latch circuit comprising;

a plurality of fuses each operative to store a respective fail address bit value,

a plurality of signal lines each associated with a respective one of said further values,

a plurality of switches each having an input terminal coupled to a corresponding one of said plurality of fuses, a control terminal coupled to an associated one of said plurality of signal lines, and an output terminal, and

a plurality of latch circuits each having a first input coupled to said output of at least a corresponding two of said plurality of switches and a second input coupled to a pre-charge line, such that when a signal is delivered over a respective one of said plurality of signal lines to each control terminal of associated ones of said plurality of switches, a respective one of said plurality of fail address bit values is delivered to said first input of each of said plurality of latch circuits from one of its corresponding fuses, and when a pre-charge signal is then delivered over said pre-charge line to each second input of said plurality of latch circuits, each of said plurality of latch circuits delivers its respective fail address bit value to said bit line controller;

said bit line controller activating a column of said memory array corresponding to said column address value when a fail address comprised of said fail address bit values differs from said column address value, said bit line controller activating a redundant column of said memory array when said fail address is said column address value.

22. The circuit of claim 21 wherein said plurality of fuses store fail address bit values representing at least two column addresses.

23. The circuit of claim 21 wherein said plurality of signal lines comprises four signal lines each representing a respective value of a two-bit long portion of said row address.

24. The circuit of claim 21 wherein said plurality of switches comprises a transistor and said control terminal comprises a gate terminal.

25. The circuit of claim 21 wherein said first input of each of said plurality of latch circuits latch circuit receives fail address bit values representing one of at least two column addresses.

26. The circuit of claim 21 wherein said first input of each of said plurality of latch circuits is coupled to up to four of said plurality of switches.

27. A memory circuit comprising:

a memory array;

a control circuit operable to receive at least one row address value and at least one column address value;

a word line controller operable to receive said row address value from said control circuit and to activate a row of said memory array corresponding to said row address value;

a bit line controller operable to receive said column address value from said control circuit;

a generator circuit operable to receive said row address value address value from said control circuit and to generate a further value based on a two-bit long portion of said row address value; and

a fuse latch circuit comprising;

a plurality of fuses each operative to store a respective fail address bit value, said plurality of fuses store fail address bit values representing at least up to four column addresses;

four signal lines each representing a respective value of said further values;

a plurality of transistor switches each having an input terminal coupled to a corresponding one of said plurality of fuses, a control terminal coupled to an associated one of said plurality of signal lines, and an output terminal; and

a plurality of latch circuits each having a first input coupled to said output of up to a corresponding four of said plurality of switches and a second input coupled to a pre-charge line, such that when a signal is delivered over a respective one of said plurality of signal lines to each gate terminal of associated ones of said plurality of switches, a respective one of said plurality of fail address bit values is delivered to said first input of each of said plurality of latch circuits from one of its corresponding fuses, and when a pre-charge signal is then delivered over said pre-charge line to each second input of said plurality of latch circuits, each of said plurality of latch circuits delivers its respective fail address bit value.