Digital predistorter for a wideband power amplifier and adaptation method

• US 20040179629A1
• Filed: 12/24/2003
• Published: 09/16/2004
• Est. Priority Date: 12/24/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, Ki-Hwan, Song, Yoo-Seung
• Granted Patent: US 7,333,559 B2
• Time in Patent Office: Days
• US Class Current: 375/296
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 2201/3224 Predistortion being done for compensating memory effects
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H04L 27/368 adaptive predistortion

Abstract

An apparatus and method for eliminating the spurious signal of a non-linear amplifier in a base station transmitter of a mobile communication system are provided. A digital predistorter includes first and second predistorters, each having a memoryless non-linearity part using a look-up table and a memory non-linearity part using an finite impulse response (FIR) filter. The first predistorter adaptively updates the look-up tables, while the second predistorter adaptively updates the filtering coefficients of the FIR filters. According to another embodiment of the present invention, a digital predistorter has a memoryless non-linearity part using a look-up table and a memory non-linearity part using an FIR filter, and adaptively updates the look-up table and the filtering coefficients of the FIR filter.

Claims

1. A digital predistortion apparatus for predistorting an input digital signal to compensate for memoryless and memory non-linearities of a wideband power amplifier, comprising:

a first predistorter for receiving the digital signal, the first predistorter being connected to the power amplifier through a digital to analog converter (DAC) and a frequency upconverter and including a first memoryless non-linearity part for compensating for the memoryless non-linearity using a first look-up table (LUT) and a first memory non-linearity part for compensating for the memory non-linearity using a first finite impulse response (FIR) filter; and

a second predistorter for receiving an feedback signal from the power amplifier through a frequency downconverter and an analog to digital converter (ADC), the second predistorter including a second memoryless non-linearity part for compensating for the memoryless non-linearity using a second LUT having the same values as the first LUT and a second memory non-linearity part for compensating for the memory non-linearity using a second FIR filter having the same filtering coefficients as the first FIR filter,

wherein the first predistorter directly updates the first LUT and the second predistorter indirectly updates the first FIR filter using the second FIR filter.

2. The digital predistortion apparatus of claim 1, wherein the first predistorter adaptively updates the first LUT using an input single-tone digital signal.

3. The digital predistortion apparatus of claim 2, wherein the first predistorter updates the first LUT using a secant algorithm expressed as

4. The digital predistortion apparatus of claim 1, wherein the first memoryless non-linearity part comprises:

a first amplitude calculator for determining an address in the first LUT by calculating the amplitude of the input digital signal;

a first multiplier for multiplying a value read from the determined address of the first LUT by the input digital signal and outputting the product to the first memory non-linearity part;

a first delay for delaying the input digital signal by a predetermined time; and

an first adaptation controller for updating the first LUT by comparing the input digital signal with the feedback signal.

5. The digital predistortion apparatus of claim 1, wherein the first predistorter adaptively updates the filtering coefficients of the second FIR filter using an input wideband digital signal.

6. The digital predistortion apparatus of claim 5, wherein the second predistorter updates the filtering coefficients of the second FIR filter according to a Normalized Least mean Square (NLMS) algorithm expressed as

7. The digital predistortion apparatus of claim 1, wherein the second memoryless non-linearity part comprises:

a second amplitude calculator for determining an address in the second LUT by calculating the amplitude of the feedback signal received from the power amplifier through the frequency downconverter and the ADC; and

a second multiplier for multiplying the feedback signal by a value read from the decided address of the second LUT and outputting the product to the second memory non-linearity part;

wherein the second memory non-linearity part comprises;

a second delay for delaying a signal received from the first predistorter by a predetermined time; and

a second adaptation controller for updating the filtering coefficients of the second FIR filter by comparing the signal received from the multiplier with a filtered signal received from the second FIR filter.

8. A method of adapting a digital predistortion apparatus for predistorting an input digital signal to compensate for the memoryless and memory non-linearities of a wideband power amplifier that amplifies the digital signal, the digital predistortion apparatus comprising a first predistorter for receiving the digital signal, the first predistorter being connected to the power amplifier through a digital to analog converter (DAC) and a frequency upconverter and including a first memoryless non-linearity part for compensating for the memoryless non-linearity and a first memory non-linearity part for compensating for the memory non-linearity, and a second predistorter for receiving an feedback signal from the power amplifier through a frequency downconverter and an analog to digital converter (ADC), the second predistorter including a second memoryless non-linearity part for compensating for the memoryless non-linearity and a second memory non-linearity part for compensating for the memory non-linearity, the method comprising the steps of:

(1) receiving a single-tone training signal at the digital predistortion apparatus and adaptively updating a first look-up table (LUT) of the first memoryless non-linearity part;

(2) applying the update of the first LUT to a second LUT of the second memoryless non-linearity part;

(3) receiving a wideband training signal at the digital predistortion apparatus and adaptively updating filtering coefficients of a second finite impulse response (FIR) filter of the second memory non-linearity part; and

(4) applying the updated filtering coefficients to a first FIR filter of the first memory non-linearity part.

9. The method of claim 8, wherein the step (1) is performed until the update degree of the first LUT is at a predetermined threshold or below.

10. The method of claim 8, wherein the step (3) is performed until the update degree of the filtering coefficients is at a predetermined threshold or below.

11. The method of claim 8, wherein the steps (1) to (4) are repeated in every predetermined period.

12. A digital predistorter for predistorting an input digital signal to compensate for the memoryless and memory non-linearities of a wideband power amplifier that amplifies the digital signal, comprising:

a memoryless non-linearity part for compensating for the memoryless non-linearity using a look-up table (LUT) and adapting the LUT using a feedback signal from the power amplifier; and

a memory non-linearity part for compensating for the memory non-linearity using a finite impulse response (FIR) filter and adapting filtering coefficients of the FIR filter using the feedback signal,

the digital predistorter being coupled to the power amplifier through a digital to analog converter (DAC) and a frequency upconverter, and predistorting the digital signal using the feedback signal received from the power amplifier through a frequency downconverter and an analog to digital converter (ADC).

13. The digital predistorter of claim 12, wherein the LUT is adaptively updated using an input single-tone digital signal.

14. The digital predistorter of claim 13, wherein the LUT is updated by using secant algorithm expressed as

15. The digital predistorter of claim 12, wherein the filtering coefficients are adaptively updated using an input wideband digital signal.

16. The digital predistorter of claim 15, wherein the filtering coefficients are updated according to a Normalized Least mean Square (NLMS) algorithm expressed as

17. A method of adapting a digital predistorter connected to a wideband power amplifier through a digital to analog converter (DAC) and a frequency upconverter, for predistorting an input digital signal using a feedback signal received from the power amplifier through a frequency downconverter and an analog to digital converter (ADC) to compensate for the memoryless and memory non-linearities of the power amplifier that amplifies the digital signal, the digital predistorter comprising a memoryless non-linearity part for compensating for the memoryless non-linearity using a look-up table (LUT) and adapting the LUT using a feedback signal from the power amplifier, and a memory non-linearity part for compensating for the memory non-linearity using a finite impulse response (FIR) filter and adapting filtering coefficients of the FIR filter using the feedback signal, the method comprising the steps of:

(a) receiving a single-tone training signal at the digital predistorter and adaptively updating the LUT of the memoryless non-linearity part; and

(b) receiving a wideband training signal at the digital predistorter and adaptively updating the filtering coefficients of the FIR filter in the memory non-linearity part.

18. The method of claim 17, wherein the step (a) is performed until the update degree of the LUT is at a predetermined threshold or below.

19. The method of claim 17, wherein the step (b) is performed until the update degree of the filtering coefficients is at a predetermined threshold or below.

20. The method of claim 17, wherein the steps (a) and (b) are repeated in every predetermined period.