Surface micromachining process for manufacturing electro-acoustic transducers, particularly ultrasonic transducers, obtained transducers and intermediate products

• US 20040180466A1
• Filed: 05/07/2004
• Published: 09/16/2004
• Est. Priority Date: 05/09/2001
• Status: Active Grant

• Current Assignee: Esaote SpA, Consiglio Nazionale Delle Ricerche (Repubblica Italiana), Universita Degli Studi Di Cagliari
• Original Assignee: Esaote SpA, Consiglio Nazionale Delle Ricerche (Repubblica Italiana), Universita Degli Studi Di Cagliari
• Inventors: Cianci, Elena, Foglietti, Vittorio, Memmi, Daniele, Pappalardo, Massimo, Caliano, Giosue
• Granted Patent: US 7,074,634 B2
• Time in Patent Office: Days
• US Class Current: 438/53
• CPC Class Codes: H04R 19/00 Electrostatic transducers

Abstract

This invention relates to a surface micromachining process for manufacturing Electro-acoustic transducers, particularly ultrasonic transducers, said transducers comprising a silicon semiconductor substrate (1), on an upper surface of which one or more membranes (18) of resilient materials are supported by a structural layer (11) of insulating materiel, rigidly connected to said semiconductor substrate (1), said resilient material having a Young'"'"'s modulus not lower than 50 GPa, said membranes (18) being metallised, said transducers including one or more lower electrodes (23, 25), rigidly connected to said semiconductor substrate (1), the process being characterised in that said structural layer (11) includes silicon monoxide. The invention further relates to an Electro-acoustic transducer, particularly an ultrasonic transducer, characterised in that the insulating material of the structural layer (11) is silicon monoxide. The invention also relates to an intermediate product for utilisation in said process for realising Electro-acoustic transducers, particularly ultrasonic transducers.

Claims

1. A surface micromachining process for manufacturing Electro-acoustic transducers, particularly ultrasonic transducers, said transducers comprising a silicon semiconductor substrate (1), on an upper surface of which one or more membranes (18) of resilient materials are supported by a structural layer (11) of insulating material, rigidly connected to said semiconductor substrate (1), said resilient material having a Young'"'"'s modulus not lower than 50 GPa, said membranes (18) being metallised, said transducers including one or more lower electrodes (23, 25), rigidly connected to said semiconductor substrate (1), the process comprising the following steps:

A. providing a silicon semiconductor substrate (1),

B. realising an intermediate product comprising;

a sacrificial layer (8, 8′

), and

a structural layer (11) of insulating material,

rigidly connected to an upper surface of said silicon semiconductor substrate (1), the surfaces of said sacrificial layer (8, 8′

) and of said structural layer (11) not in contact with said substrate (1) being substantially co-planar,

C. depositing a layer (15) of said resilient material on said sacrificial layer (8, 8′

) and on said structural layer (11), and

D. releasing said membranes (18) of said resilient material by removing said sacrificial layer (8, 8′

) from the product obtained according to said step C.,

said process being characterised in that said structural layer (11) includes silicon monoxide.

2. A process according to claim 1, characterised in that all of the steps of the process are carried out at temperatures not higher than 600°

C.

3. A process according to claim 2, characterised in that all of the steps of the process are carried out at temperatures not higher than 530°

C.

4. A process according to any one of the preceding claims, characterised in that said resilient material has a value of the Young'"'"'s modulus not lower than 100 GPa.

5. A process according to claim 4, characterised in that said resilient material comprises silicon nitride.

6. A process according to claim 4, characterised in that said resilient material comprises crystalline silicon.

7. A process according to any one of the preceding claims, characterised in that said sacrificial material (8′

) comprises chromium.

8. A process according to any one of claims 1 to 6, characterised in that said sacrificial material (8) comprises an organic polymer selected among the group comprising polyamides and polymers of benzocyclobutene and its derivatives.

9. A process according to claim 8, characterised in that said organic polymer comprises polyamide.

10. A process according to claim 9, characterised in that said polyamide comprises N-methyl-2-pyrolidone.

11. A process according to any one of the preceding claims, characterised in that said step D comprises the following successively ordered sub-steps:

D.1 realising one or more apertures or vias (16) on said layer (15) of resilient material, adapted to enable accessing the sacrificial layer (8) from outside, and

D.2 thermally treating by annealing the product obtained according to said step C.

12. A process according to claim 9, characterised in that, during execution of said sub-step D.2, the product obtained according to said step C is heated to a temperature in the range of 490°

C. to 530°

C.

13. A process according to claim 11 or 12, when considered as dependant on any one of claims 8 to 10, characterised in that said sub-step D.2 has a duration adapted to completely eliminate the organic polymer existing in the product obtained according to said step C.

14. A process according to any one of the claims 11 to 13, characterised in that said step D further comprises, indifferently before or after said sub-step D.1 or D.2, the following sub-step:

D.3 chemically etching said sacrificial layer.

15. A process according to claim 14, when considered as dependant on claim 7, characterised in that said sub-step D.3 comprises imaging the product in a wet etching solution for etching chromium.

16. A process according to claim 14, when considered as dependant on any one of claims 8 to 10, characterised in that said sub-step D.3 comprises imaging the product obtained according to said step C in a solution comprising sulphuric acid (H₂SO₄).

17. A process according to claim 16, characterised in that said solution utilised in said sub-step D.3 further comprises hydrogen peroxide (H₂O₂).

18. A process according to claim 17, characterised in that said solution utilised in said sub-step D.3 is a solution 7:

3 of sulphuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂).

19. A process according to any one of claims 14 to 18, characterised in that, when said sub-step D.3 is subsequent to said sub-step D.2, said step b further comprises, after said sub-step D.3, the following sub-step:

D.4 thermally treating by annealing the product obtained according to said step D.

20. A process according to claim 19, characterised in that, during execution of said sub-step D.4, the product obtained according to said step C is heated to a temperature in the range of 490°

C. to 530°

C.

21. A process according to any one of claims 11 to 20, characterised in that the total duration of the annealing operation for the product obtained according to said step C is adapted to make the intrinsic compression stress of the membranes (18) no higher than 10 MPa.

22. A process according to claim 21, characterised in that the total duration of the annealing operation for the product obtained according to said step C is adapted to make the intrinsic tensile stress of the membranes (18) comprised in the range of 10 MPa to 50 MPa.

23. A process according to any one of the preceding claims, characterised in that said vias (16) are external to the locations of said membranes (18) and are positioned at a distance therefrom adapted to introduce substantially negligible stress gradients, said sacrificial layer (8) comprising channels (7) to connect the positions of said vias (16) to the locations of said membranes (18).

24. A process according to claim 7, characterised in that said step B comprises the following successively ordered sub-steps:

B.1 depositing a chromium comprising layer (28) on said upper surface of the semiconductor substrate (1),

B.2 defining configurations or patterns in said chromium comprising layer (28) by realising cavities in said chromium comprising layer (28), and

B.3 filling said cavities in said chromium comprising layer (28) by depositing silicon monoxide therein.

25. A process according to any one of the preceding claims 8 to 10, characterised in that said step B comprises the following successively ordered sub-steps:

B.1 applying a layer (2) comprising said organic polymer upon said upper surface of the semiconductor substrate (1),

B.2 defining configurations or patterns in said layer (2) comprising said organic polymer by realising cavities (10) in said in said layer comprising said organic polymer, and

B.3 filling said cavities (10) in said layer (2) comprising said organic polymer by depositing silicon monoxide therein.

26. A process according to claim 24 or 25, characterised in that, during said sub-step B.3, the silicon monoxide is deposited by thermal evaporation.

27. A process according to claim 24 or 26, when considered as dependant on claim 24, characterised in that said sub-step B.2 comprises an optical lithographic process performed on said chromium comprising layer (28) by utilising a masking layer of photographically patterned optical resist and a wet chemical etching of the chromium.

28. A process according to claim 25 or 26, when considered as dependant on claim 25, characterised in that said sub-step B.2 comprises a dry reactive ion etching (RIE) operation performed on said layer (2) comprising said organic polymer by utilising a masking layer (9) of photolithographically patterned optical resist.

29. A process according to claim 27 or 28, characterised in that said step B further comprises, after said sub-step B.3, the following sub-steps:

B.4 chemically etching said silicon monoxide by utilising a wet etching process,

B.5 removing said optical resist.

30. A process according to claim 27 or 28, characterised in that said step B further comprises, after said sub-step B.3, the following sub-step:

B.4 removing the silicon monoxide deposited upon said optical resist by means of a lift off process.

31. A process according to claim 30, characterised in that said sub-step B.4 comprises dissolving said optical resist by means of an acetone and ultrasound dissolving process.

32. A process according to any one of claims 8 to 10, characterised in that said step B comprises the following successively ordered sub-steps:

B.1 depositing a silicon monoxide comprising layer on said upper surface of the semiconductor substrate (1),

B.2 defining configurations or patterns (11) in said silicon monoxide comprising layer,

B.3 applying a layer (2) comprising said organic polymer upon said upper surface of the semiconductor substrate (1), provided with silicon monoxide,

B.4 performing a chemical-mechanical polishing operation adapted to realise said intermediate product.

33. A process according to claim 32, characterised in that during said sub-step B.1, the silicon monoxide is deposited by thermal evaporation.

34. A process according to claim 32 or 33, characterised in that said sub-step B.2 comprises a dry reactive ion etching (RIE) operation performed on said silicon monoxide comprising layer by utilising a masking layer of photolithographically patterned optical resist.

35. A process according to any one of the preceding claims, characterised in that, during said step C, said resilient material is deposited by a plasma enhanced chemical vapour deposition process (PECVD).

36. A process according to claim 11, characterised in that it further comprises, after said step D, the following step:

E. closing said vias (16) by

deposition of silicon monoxide adapted to fill up said vias (16),

optical lithography, and

RIE etching of the silicon monoxide deposited on said membranes (18).

37. A process according to claim 36, characterised in that during said step E, the silicon monoxide is deposited by thermal evaporation.

38. A process according to any one of the preceding claims, characterised in that it further comprises, before said step B, the following step:

F. realising a lower electrode (25) on the upper surface of the semiconductor substrate (1) in positions corresponding to each area in which said membranes (18) are realised during said step D.

39. A process according to claim 38, characterised in that said step F comprises the following sub-steps:

F.1 depositing an insulating layer (26) on the upper surface of the semiconductor substrate (1),

F.2 depositing a conductive layer upon said insulating layer (26),

F.3 defining configurations or patterns in said conductive layer.

40. A process according to claim 39, characterised in that said insulating layer (26) comprises thermal silicon dioxide SiO₂, said conductive layer comprises evaporation deposited chromium, and said sub-step F.3 comprises an optical lithographic process performed on said conductive layer by utilising a masking layer formed by a photolithographically patterned optical resist and a chemical wet etching of the chromium.

41. A process according to any one of claims 38 to 40, characterised in that said step F further realises a film (27) for protection of said lower electrodes (25).

42. A process according to claim 41, characterised in that said protection film (27) is realised by growing a film of silicon nitride SiN by means of a PECVD technique.

43. A process according to any one of claims 1 to 37, characterised in that it further comprises the following step:

F. realising one or more lower electrodes (23) by metallisation of a lower surface of said semiconductor substrate (1).

44. A process according to any one of the preceding claims, characterised in that it further comprises the following step:

G. metallising said membranes (18)

45. A process according to any one of the preceding claims, characterised in that said silicon semiconductor substrate (1) is a p-type doped silicon substrate having a resistivity no higher than 1 Ω

.cm, preferably no higher than 2 Ω

.cm.

46. A process according to any one of the preceding claims, characterised in that said silicon monoxide comprising structural layer (11) has a thickness in the range of 100 nm to 1000 nm, preferably in the range of 400 nm to 600 nm, and in that said membranes (18) of said resilient material have a thickness no higher than 1000 nm, preferably no higher than 600 nm.

65. An intermediate product according to any one of the preceding claims, characterised in that it further comprises a layer (15) of resilient material having a Young'"'"'s modulus no lower than 50 GPa, superimposed on said sacrificial layer (8) and on said structural layer (11).

66. An intermediate product according to claim 65, characterised in that said resilient material has a value of the Young'"'"'s modulus no lower than 100 GPa.

67. An intermediate product according to claim 65 or 66, characterised in that said resilient material comprises silicon nitride.

68. An intermediate product according to claim 65 or 66, characterised in that said resilient material comprises crystalline silicon.

69. An intermediate product according to any one of claims 65 to 68, characterised in that said layer (15) of resilient material has a thickness no higher than 1000 nm, preferably no higher than 600 nm.

47. An Electro-acoustic transducer, particularly an ultrasonic transducer, comprising a silicon semiconductor substrate (1), on an upper surface of which one or more membranes (18) of resilient materials are supported by a structural layer (11) of insulating material, rigidly connected to said semiconductor substrate (1), said resilient material having a Young'"'"'s modulus not lower than 50 GPa, said membranes (18) being metallised , said transducer including one or more lower electrodes (23, 25), rigidly connected to said semiconductor substrate (1), said transducer being characterised in that said insulating material is silicon monoxide.

48. A transducer according to claim 47, characterised in that said resilient material has a value of the Young'"'"'s modulus no lower than 100 GPa.

49. A transducer according to claim 48, characterised in that said resilient material comprises silicon nitride.

50. A transducer according to claim 48, characterised in that said resilient material comprises crystalline silicon.

51. A transducer according to any one of claims 47 to 50, characterised in that said membranes (18) have an intrinsic compression stress no higher than 10 MPa.

52. A transducer according to claim 51, characterised in that said membranes (18) have an intrinsic tensile stress in the range of 10 MPa to 50 MPa.

53. A transducer according to any one of claims 47 to 52, characterised in that said silicon monoxide comprising structural layer (11) has a thickness in the range of 100 nm to 1000 nm, preferably in the range of 400 nm to 600 nm, and in that said membranes (18) of said resilient material have a thickness no higher than 1000 nm, preferably no higher than 600 nm.

54. A transducer according to any one of claims 47 to 52, characterised in that said one or more lower electrodes (25) are realised on the upper surface of said semiconductor substrate (1) in positions corresponding to each of said areas underlying said membranes (18).

55. A transducer according to claim 54, characterised in that it further comprises an insulating layer (26), underlying said lower electrodes (25), on the upper surface of said semiconductor substrate (1).

56. A transducer according to claim 55, characterised in that said insulating layer (26) comprises silicon dioxide SiO₂ and said conductive layer comprises chromium.

57. A transducer according to any one of claims 54 to 56, characterised in that it further comprises a film (27) for protection of said lower electrodes (25).

58. A transducer according to claim 57, characterised in that said protection film (27) comprises silicon nitride SiN.

59. A transducer according to any one of claims 47 to 53, characterised in that said one or more lower electrodes are realised by means of a metallised layer (23) on said lower surface of the semiconductor layer (1).

60. An intermediate product for realising Electro-acoustic transducers, particularly ultrasonic transducers, comprising

a sacrificial layer (8), and

a structural layer (11) of insulating material,

rigidly connected to an upper surface of said silicon semiconductor substrate (1), the surfaces of said sacrificial layer (8) and of said structural layer (11) not in contact with said substrate (1) being substantially co-planar, said intermediate product being characterised in that said structural layer (11) comprises silicon monoxide.

61. An intermediate product according to claim 60, characterised in that said sacrificial layer (8′

) comprises chromium.

62. An intermediate product according to claim 60, characterised in that said sacrificial material (8) comprises an organic polymer selected among the group comprising polyamides and polymers of benzocyclobutene and its derivatives.

63. An intermediate product according to claim 62, characterised in that said organic polymer comprises polyamide.

64. An intermediate product according to any one of claims 60 to 63, characterised in that said sacrificial layer (8) and said structural layer (11) have a thickness in the range of 100 nm to 1000 nm, preferably in the range of 400 nm to 600 nm.