Method of forming an element of a microelectronic circuit

• US 20040180499A1
• Filed: 03/12/2003
• Published: 09/16/2004
• Est. Priority Date: 03/12/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doyle, Brian S., Murthy, Anand S.
• Granted Patent: US 6,972,228 B2
• Time in Patent Office: Days
• US Class Current: 438/269
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02387 Group 13/15 materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/125 Quantum wire structures
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01S 5/341 Structures having reduced dimensionality, e.g. quantum wires

Abstract

A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

Claims

1. A method of forming an element of a microelectronic circuit, comprising:

forming a sacrificial layer having a lower surface on an upper surface of a support layer;

forming a height-defining layer having a lower surface on an upper surface of the sacrificial layer;

removing the sacrificial layer so that a gap is defined between the upper surface of the support layer and the lower surface of the height-defining layer; and

growing a monocrystalline semiconductor material from a nucleation site at least partially through the gap with a height of the semiconductor material being defined by a height of the gap.

2. The method of claim 1, further comprising:

removing the height-defining layer; and

patterning the semiconductor material.

3. The method of claim 2, wherein the support layer is an insulator and the semiconductor material is patterned into an elongate wire element.

4. The method of claim 3, further comprising:

doping the wire element; and

forming a conductive gate over and along opposing sides of the wire element.

5. The method of claim 1, wherein the semiconductor material is at least one of silicon (Si), germanium (Ge), silicon germanium (Si_xGe_y), gallium arsenide (GaAs), InSb, GaP, GaSb and carbon.

6. The method of claim 1, further comprising:

forming the support layer over a portion of a semiconductor monocrystalline substrate, an open portion of the semiconductor monocrystalline substrate having the nucleation site.

7. A method of forming an element of a microelectronic circuit, comprising:

forming a dielectric layer on a semiconductor monocrystalline substrate;

forming a structure on the semiconductor monocrystalline substrate, having a height-defining layer, a gap being defined between an upper surface of the support layer and a lower surface of the height-defining layer; and

growing a monocrystalline semiconductor material from a nucleation site on the semiconductor monocrystalline substrate, the semiconductor material growing at least partially through the gap with a height of the semiconductor material being defined by a height of the gap.

8. The method of claim 7, further comprising:

removing the height-defining layer; and

patterning the semiconductor material.

9. The method of claim 8, wherein the support layer is an insulator and the semiconductor material is patterned into an elongate wire element.

10. The method of claim 9, further comprising:

doping the wire element; and

forming a conductive gate over and along opposing sides of the wire element.

11. A method of forming an element of a microelectronic circuit, comprising:

forming an dielectric layer horizontally over a horizontal semiconductor monocrystalline substrate;

forming a sacrificial layer having a horizontal lower surface on a horizontal upper surface of the dielectric layer, the sacrificial layer being of a different material than the dielectric layer;

forming a height-defining layer having a lower surface on a horizontal upper surface of the sacrificial layer, the height-defining layer being of a different material than the sacrificial layer;

removing the sacrificial layer with an etchant that selectively removes the material of the sacrificial layer over the materials of the dielectric layer and the height-defining layer, to leave a gap between the upper surface of the dielectric layer and the lower surface of the height-defining layer, the height-defining layer being maintained in a vertical position relative to the dielectric layer by a support piece on the semiconductor monocrystalline substrate;

growing a monocrystalline semiconductor material from a nucleation site on the semiconductor monocrystalline substrate, the monocrystalline semiconductor material growing horizontally through the at least part of the gap to form a semiconductor layer with a vertical height thereof being limited by a vertical height of the gap.

12. The method of claim 11, further comprising:

removing the height-defining layer to expose the semiconductor layer; and

patterning the semiconductor material to have a select horizontal length.

13. The method of claim 12, wherein the semiconductor layer is patterned into a wire element having a select horizontal length and having an elongate width.

14. The method of claim 13, further comprising:

doping the wire element; and

forming a conductive gate over and along opposing sides of the wire element.

15. The method of claim 11, wherein the semiconductor material grows vertically past the dielectric layer before growing horizontally into the gap.