System and method for testing memory during boot operation idle periods

• US 20040181656A1
• Filed: 03/10/2003
• Published: 09/16/2004
• Est. Priority Date: 03/10/2003
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Alexander, Marc D., Stern, Jonathan T.
• Granted Patent: US 7,162,625 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

The present invention discloses an information handling system that reduces POST time in a boot operation. The information handling system includes a processor, a memory and a BIOS unit. The BIOS also includes memory test pointer and a test block size indicator. During the POST routine, the BIOS tests at least one test block during at least one idle period.

Claims

1. An information handing system comprising:

a processor;

a Random Access Memory (RAM) in communication with the processor;

a Basic Input/Output System (BIOS) in communication with the processor, the BIOS having a memory test pointer and a test block size indicator;

the BIOS operable to perform a Power On Self Test (POST) routine and further operable to test at least one test block of the RAM during at least one idle period during the POST routine.

2. The information handing system of claim 1 further comprising the test pointer operable to indicate the portion of the RAM to be tested.

3. The information handling system of claim 1 further comprising a test block period indicator.

4. The information handling system of claim 1 further comprising the test block period set at approximately one hundred microseconds (100 us).

5. The information handing system of claim 1 further comprising the test block period set between the range of 50 microseconds and 250 microseconds.

6. The information handling system of claim 1 wherein at least one idle period comprises a spin-up period for an associated hard drive.

7. The information handling system of claim 1 wherein at least one idle period comprises an initialization period for an association Universal Serial Bus (USB) device.

8. The information handling system of claim 1 wherein at least one idle period comprises an initialization period for an associated optical drive.

9. The information handling system of claim 1 wherein at least one idle period comprises an initialization period for an associated storage drive.

10. The information handling system of claim 1 wherein the BIOS further comprises a test block period and the BIOS further operable to calibrate the test block size indicator based upon the test block period.

11. The information handling system of claim 1 further comprising the BIOS operable to:

test a plurality of test blocks of the RAM during a first idle period; and

test a plurality of test blocks of the RAM during a second idle period.

12. The information handling system of claim 1 further comprising the BIOS operable to:

test a first test block during an idle period;

determine whether the idle period has ended; and

test a second test block if the BIOS determines that the idle period has not ended.

13. A basic input output system (BIOS) comprising:

a test pointer;

a memory test block size indicator having a pre-selected period;

a memory test block period indicator;

the BIOS operable to calibrate the test block size indicator for the pre-selected period prior to running a Power On Self Test (POST) routine; and

the BIOS further operable to test at least one memory test block during at least one idle period during the POST routine.

14. The BIOS of claim 13 further comprising the pre-selected period set between the range of 50 microseconds and 250 microseconds.

15. The BIOS of claim 13 further comprising the memory test block size indicator showing the amount of memory to be tested in each memory test block.

16. The BIOS of claim 13 wherein the idle period comprises a spin-up period of an associated hard drive.

17. The BIOS of claim 13 wherein the idle period comprises an initialization period for an associated Universal Serial Bus device.

18. A method for reducing Power On Self Test (POST) routine times for an information handling system comprising:

providing a basic input/output system (BIOS) having a test pointer, a test block size indicator, and a test block period indicator;

calibrating the test block size indicator prior to a POST routine; and

testing at least one test block during at least one idle period during the POST routine.

19. The method of claim 18 further comprising testing at least one memory block during a hard drive spin-up period during the POST routine.

20. The method of claim 18 further comprising testing at least one memory block during an initialization period for an associated component during the POST routine.