Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code

• US 20040181732A1
• Filed: 03/04/2004
• Published: 09/16/2004
• Est. Priority Date: 07/12/1999
• Status: Active Grant

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Inventors: Fitzpatrick, Kelly, McEwen, Peter
• Granted Patent: US 7,089,483 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 2020/1863 wherein the Viterbi algorithm is used for decoding the error correcting code
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.

Claims

1. A two-stage detector for a partial response channel having a known channel transfer function;

the channel having a channel code encoder for encoding information sequences into code words in accordance with a predetermined channel code enabling detection of any single occurrence within a code word of an error-event of a list of error-events known likely to occur on the partial response channel, the list of error-events being characterized in that adding any error-event from the list to any code word of the channel code will not produce another code word;

the channel code including but not being limited to modulation codes concatenated with systematic parity codes, the channel code not including matched-spectral-null codes and linear block codes with Hamming distance greater than a number of bit errors in each of the error-events on the list;

the two-stage detector including;

a channel sampler for providing samples of the partial response channel equalized in accordance with a time domain response characteristic of the partial response channel;

a first-stage detector connected to receive the samples from the channel sampler, the first-stage detector being matched to characteristics of the partial response channel and not to the channel code, for putting out unchecked bit estimates; and

,

a second-stage post-processor connected to receive the unchecked bit estimates and the samples;

the post-processor including a sequence checker for detecting error-events in the unchecked code words, and a sequence corrector for correcting the most-likely combination of error-events based on channel metric information generated from the samples, the unchecked bit estimates, the known channel transfer function, and the channel code, and for putting out checked bit estimates.

2. The two-stage detector for a partial response channel set forth in claim 1 wherein partial response channel comprises a magnetic recording channel, and wherein the transfer function for the partial response channel is a fourth-order polynomial selected for near optimal performance at high recording densities on the magnetic recording channel and comprising 1.75+D−

D²−

1.25D³−

0.5D⁴, where D represents a unit delay operator.

3. The two-stage detector for a partial response channel set forth in claim 1 wherein the channel code encoder includes a modulation code encoder, a precoder, and a parity code encoder, and wherein parity bits are calculated by the parity code encoder on non-return-to-zero (NRZ) bits following precoding, such that the parity bits are polarity dependent.

4. The two-stage detector for a partial response channel set forth in claim 1 wherein the channel code encoder includes a modulation code encoder, a parity code encoder, and a precoder, and wherein the parity bits are calculated on non-return-to-zero-inverse (NRZI) bits before preceding, such that after passing through the precoder the NRZI bits are polarity independent.

5. The two-stage detector for a partial response channel set forth in claim 3 wherein the list of error events includes NRZ error events:

+, +−

, +−

+, and +0+.

6. The two-stage detector for a partial response channel set forth in claim 4 wherein the precoder operates in accordance with 1/(1+D) modulo 2, and the list of error events includes NRZI error events:

++, +0−

, +00+, and ++++.

7. The two-stage detector for a partial response channel set forth in claim 4 wherein the precoder operates in accordance with 1/(1+D²) modulo 2, and the list of error events includes NRZI error events:

+0+, +−

+−

, +−

0−

+, and +000+.

8. The two-stage detector for a partial response channel set forth in claim 4 wherein the channel code comprises a modulation code concatenated with a parity code, the modulation code having one of rate 48/49 and rate 50/51.

9. The two-stage detector for a partial response channel set forth in claim 1 wherein the channel code encoder comprises a modulo-n parity code encoder, and wherein a number of parity bits generated by the parity code encoder is a smallest integer greater than log₂(n) and wherein the parity bits are calculated as a weighted sum modulo-n of the bits in a code word block using a preselected weighting vector.

10. The two-stage detector for a partial response channel set forth in claim 9 wherein the channel code encoder comprises a modulation code encoder concatenated with the modulo-n code parity encoder.

11. The two-stage detector for a partial response channel set forth in claim 9 wherein the modulo-n encoder generates a modulo-7 code, wherein the parity code encoder generates three parity bits, and wherein the preselected weighting vector comprises {1 2 4} repeated.

12. The two-stage detector for a partial response channel set forth in claim 1 wherein the channel code encoder comprises an interleaved parity code encoder for bit-wise interleaving at least two single parity codes into the code words.

13. The two-stage detector for a partial response channel set forth in claim 1 wherein the channel code encoder comprises a cyclic code encoder for generating a cyclic code with Hamming distance less than or equal to a number of bit errors in at least one of the error-events of the list.

14. The two-stage detector for a partial response channel set forth in claim 13 wherein the channel code encoder comprises a modulation code encoder concatenated with a cyclic code encoder.

15. The two-stage detector for a partial response channel set forth in claim 13 wherein the cyclic code encoder employs a degree 3 primitive irreducible polynomial to generate the cyclic code and further comprising a parity code encoder for generating three parity bits.

16. The two-stage detector for a partial response channel set forth in claim 1 wherein the first-stage detector comprises a detector matched to the transfer function for the partial response channel in additive white Gaussian noise.

17. The two-stage detector for a partial response channel set forth in claim 16 wherein the first-stage detector comprises a Viterbi detector.

18. The two-stage detector for a partial response channel set forth in claim 1 wherein the first-stage detector incorporates noise characteristics of the partial response channel.

19. The two-stage detector for a partial response channel set forth in claim 18 wherein the first-stage detector comprises a Viterbi detector having non-linear branch metrics.

20. The two-stage detector for a partial response channel set forth in claim 18 wherein the first-stage detector comprises a Viterbi detector for signal-dependent correlated noise.

21. The two-stage detector for a partial response channel set forth in claim 18 wherein the first-stage detector comprises a noise-predictive detector.

22. The two-stage detector for a partial response channel set forth in claim 1 wherein the sequence corrector includes correction means for correcting an error-event spanning a boundary between two adjacent code words.

23. The two-stage detector for a partial response channel set forth in claim 1 wherein the sequence corrector includes correction means for correcting a plurality of error-events within a code word.

24. The two-stage detector for a partial response channel set forth in claim 23 wherein the correction means corrects one or more error events spanning a boundary between two adjacent code words.

25. The two-stage detector for a partial response channel set forth in claim 1 wherein the partial response channel comprises a magnetic data recording and playback channel.

26. The two-stage detector for a partial response channel set forth in claim 25 wherein the magnetic data recording and playback channel comprises a rotating magnetic data storage disk, and a data write/read transducer structure coupled magnetically to a data storage surface of the rotating disk.

27. The two-stage detector for a partial response channel set forth in claim 25 wherein the magnetic data recording and playback channel comprises a lineally moving magnetic tape and a data transducer coupled magnetically to a data storage surface of the moving magnetic tape.

28. The two-stage detector for a partial response channel set forth in claim 25 wherein the magnetic data recording and playback channel has an input for receiving blocks of user data, an outer error correction code encoder for calculating and appending error correction information to each block of user data and for providing block encoded user data to the channel code encoder, and further comprising an outer error correction code decoder for receiving decoded output bit sequence estimates from the channel code decoder, for detecting and correcting user block errors based upon the appended error correction information.

29. The two-stage detector for a partial response channel set forth in claim 1 being formed as a single large scale integrated circuit adapted to check and correct sequences based on a selected one of a plurality of channel codes supported by said integrated circuit, and including switching means for selecting checking and correcting sequences in accordance with said selected one of the plurality of channel codes.

30. The two-stage detector for a partial response channel set forth in claim 29 wherein the plurality of channel codes supported by said integrated circuit includes a single bit parity code, a two bit interleaved parity code, and a three-bit modulo-n cyclic code having a predetermined weighting vector.

31. The two-stage detector for a partial response channel set forth in claim 1 wherein the predetermined channel code is determined in accordance with a method comprising the steps set forth in claim 47.

32. A two-stage detector for a partial response channel having a known channel transfer function and including a channel code encoder for encoding information sequences into blocks of code words in accordance with a predetermined channel code enabling detection of any single occurrence within a code word of an error-event of a list of error-events known likely to occur on the partial response channel and comprising impermissible code words, the channel further including a channel sampler, the two-stage detector comprising:

a first-stage detector connected to receive samples from the channel sampler, the first-stage detector being matched to characteristics of the known channel transfer function and not to the channel code, for putting out unchecked bit estimates comprising code words, and

a second stage post-processor being connected to receive the samples and the unchecked bit estimates, for deriving detector decision metrics information from the samples, the unchecked bit estimates and the channel transfer function;

for checking and correcting multiple error-events within a single code word in accordance with the predetermined channel code and the decision metrics information; and

, for putting out post-processed code words to a channel code decoder.

33. The two-stage sampling data detector set forth in claim 32 wherein the predetermined channel code comprises one of a single bit parity code, a two bit interleaved parity code, and a three-bit modulo-7 code having weighting vector {1 2 4} repeated.

34. The two-stage sampling data detector set forth in claim 32 wherein the known channel transfer function comprises an NPR target having a discrete-time transfer function of 14+8D−

8D²−

10D³−

4D⁴, wherein D comprises a unit time delay operator.

35. The two-stage sampling data detector set forth in claim 32 wherein the predetermined channel code is derived in accordance with a method comprising the steps set forth in claim 47.

36. In a device implementing a maximum likelihood detector for use within a partial response channel having a known channel transfer function and passing user information sequences encoded into channel code blocks in accordance with a predetermined channel block code, a large scale integrated circuit comprising:

a channel sampler connected for sampling the channel and for generating raw samples,

a channel equalizer for equalizing the raw samples to the known channel transfer function to produce equalized samples,

a first-stage detector connected to receive the equalized samples from the channel sampler, the first-stage detector being matched to the known channel transfer function and not to the channel block code, for putting out unchecked bit estimates, and

a second stage post-processor being connected to receive the raw samples and the unchecked bit estimates, and including;

a parity checker for checking parity of a channel code block to determine presence of one or more error-events,

a first stage detector error metrics generator for generating first stage detector decision metrics information from the raw samples and the unchecked bit estimates in accordance with the channel transfer function;

a plurality of decision metrics filters for correlating error-events against known likely error-events to determine permissible most-likely error events in accordance with the predetermined channel block code, and

a channel code block corrector responsive to the parity checker and to the plurality of decision metrics filters, for determining a most likely error-event from a group comprising one error-event contained within a single code block, one error-event straddling two adjacent code blocks, a plurality of error-events contained within a single code block, and a plurality of error-events at least one of which straddles two adjacent code blocks, and for selecting a most-likely permissible error-event and correcting an estimated channel code block to remove the most-likely permissible error-event.

37. The large scale integrated circuit set forth in claim 36 wherein the channel sampler comprises a clocked flash analog-to-digital converter, the channel equalizer comprises a digital finite impulse response filter, and the first stage detector comprises a Viterbi detector.

38. The large scale integrated circuit set forth in claim 37 further comprising a channel code encoder for encoding user information sequences into the channel code blocks in accordance with the predetermined channel modulation code prior to passage of said blocks through said partial response channel, and a channel code decoder for decoding corrected estimated channel code blocks received from the channel code block corrector into estimated user information sequences.

39. The large scale integrated circuit set forth in claim 38 wherein the user information sequences include user information blocks and further comprising a block error correction code encoder for encoding the user information blocks in accordance with a predetermined error correction code algorithm and for appending error correction syndrome information onto the user information blocks before putting out said user information sequences to said channel code encoder, and a block error correction code decoder connected to receive estimated user information sequences from the channel code decoder, for checking said estimated sequences in accordance with estimates of said appended error correction syndrome information and for correcting erroneous sequences in accordance with said predetermined error correction code algorithm.

40. The large scale integrated circuit set forth in claim 39 embodied within a magnetic recording and playback device.

41. The large scale integrated circuit set forth in claim 40 wherein the magnetic recording and playback device comprises a hard disk drive and the partial response channel includes a rotating magnetic data storage disk.

42. The large scale integrated circuit set forth in claim 40 wherein the magnetic recording and playback device comprises a tape drive and the partial response channel includes a moving magnetic-data tape.

43. The large scale integrated circuit set forth in claim 36 wherein the known channel transfer function comprises an NPR target having a discrete-time transfer function of 14+8D−

8D²−

10D<sup>3−

4</sup>D⁴, wherein D comprises a unit time delay operator.

44. The large scale integrated circuit set forth in claim 36 wherein the predetermined channel block code comprises one of a single bit parity code, a two bit interleaved parity code, and a three-bit modulo-7 code having a weighting vector {1 2 4} repeated.

45. A method for detecting and correcting error-events within a modulation code block passing through a partial response channel having a channel transfer function including the steps of:

determining checking information for the modulation code block in accordance with a predetermined channel code selected from a group of codes essentially consisting of modulo-n codes having weighting vector {1 2 4} repeated, interleaved parity codes, and cyclic codes having a rate (R) greater than (2^p−

1−

p)/2^p−

1 where p is equal to the number of parity bits,

appending the checking information to the modulation code block to form a channel code encoded block,

passing the channel code encoded block through the partial response channel,

sampling the passed channel code encoded block to provide samples,

passing the samples through a first stage detector matched to a transfer function of the channel and not to the channel code, in order to provide unchecked bit estimates,

passing the samples and the unchecked bit estimates through a second stage post-processor for checking the unchecked bit estimates in accordance with the appended checking information, for deriving first stage detector decision metrics information from the samples, the unchecked bit estimates and the channel transfer function;

for correcting a channel code encoded block determined to include at least one error-event based upon the decision metrics information, the appended checking information and the channel code.

46. A method for detecting and correcting error-events within a modulation code block passing through a partial response channel having a channel transfer function including the steps of:

determining checking information for the modulation code block in accordance with a predetermined channel code,

appending the checking information to the modulation code block to form a channel code encoded block,

passing the channel code encoded block through the partial response channel,

sampling the passed channel code encoded block to provide samples,

passing the samples through a first stage detector matched to a transfer function of the channel and not to the channel code, in order to provide unchecked bit estimates,

passing the samples and the unchecked bit estimates through a second stage post-processor for checking the unchecked bit estimates in accordance with the appended checking information, for deriving first stage detector decision metrics information from the samples, the unchecked bit estimates and the channel transfer function;

for correcting a channel code encoded block determined to include at least two error-events within the channel code block based upon the decision metrics information, the appended checking information and the channel code.

47. A method for generating a high rate channel code for use as part of a maximum likelihood detector within a high density partial response channel having a known channel transfer function and including a channel code encoder for encoding user information sequences into code words in accordance with the high rate channel code and wherein the sampling data detector includes a channel sampler for providing samples of the partial response channel equalized in accordance with a time domain response characteristic of the partial response channel;

a first-stage detector connected to receive the samples from the channel sampler, the first-stage detector being matched to characteristics of the partial response channel and not to the channel code, for putting out unchecked bit estimates; and

, a second-stage post-processor connected to receive the unchecked bit estimates and the samples;

the post-processor including a sequence checker for detecting error-events in the unchecked code words, and a sequence corrector for correcting the most-likely combination of error-events based on channel metric information generated from the samples, the unchecked bit estimates, the known channel transfer function, and the channel code, and for putting out checked bit estimates;

the method comprising steps of;

passing a known high rate data pattern through a construct of the high density partial response channel,

accumulating a list of most likely error-events within sequences of the known high rate data pattern at a construct of the first-stage detector, and

forming the high rate channel code so that out of every pair of Euclidean squared distance nearest neighbor code words, one of the pair is disallowed as a code word if both of the pair are separated by one of the most likely error events of the list.