×

Model pattern simulation of semiconductor wafer processing steps

  • US 20040181768A1
  • Filed: 03/12/2003
  • Published: 09/16/2004
  • Est. Priority Date: 03/12/2003
  • Status: Abandoned Application
First Claim
Patent Images

1. A method of specifying a model pattern of a diffracting structure for use in semiconductor metrology, the diffracting structure to be fabricated on a semiconductor substrate employing a lithographic process, the method comprising:

  • specifying a series of process steps to be employed in fabrication of a diffracting structure on a semiconductor substrate employing a lithographic process; and

    simulating the series of process steps to produce a model pattern of the diffracting structure.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×