Poly-sealed silicide trench gate

• US 20040183129A1
• Filed: 01/29/2004
• Published: 09/23/2004
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Michael E. Cornell, Richard K. Williams, Wai Tien Chan
• Original Assignee: Michael E. Cornell, Richard K. Williams, Wai Tien Chan
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Granted Patent: US 7,075,145 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Claims

1. A power MOSFET comprising:

a substrate comprising a first trench extending from a top surface of the substrate;

a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;

an insulating layer lining the wall of the first trench; and

a gate structure comprising a metal/silicide region in the first trench and a silicon layer between the metal/silicide region and the insulating layer.

2. The power MOSFET of claim 1, wherein the substrate further comprises a second trench.

3. The power MOSFET of claim 2, wherein the metal/silicide region and the polysilicon region extend continuously from the second trench into the first trench.

4. The power MOSFET of claim 1, wherein the silicon layer surrounds the metal/silicide region so that the metal/silicide region is sealed at a top of the first trench and a bottom of the first trench.

5. The power MOSFET of claim 1, wherein the silicon layer comprises polysilicon.

6. A method for fabricating a power MOSFET comprising:

forming a first trench in a substrate;

forming an insulating layer on walls of the first trench;

depositing a first silicon layer that lines the first trench;

depositing a metal layer on the first silicon layer in the first trench;

depositing a second silicon layer on the metal layer so that the first and second silicon layers surround the metal layer; and

doping the substrate adjacent the first trench to form a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench;

7. The method of claim 6, wherein the first silicon layer comprises a conformal polysilicon layer that is between 200 Å

and 2000 Å

thick.

8. The method of claim 6, wherein the metal layer comprises a metal selected from a group consisting of tungsten, platinum, titanium, chromium, and cobalt.

9. The method of claim 6, wherein the metal layer is between 100 Å

and 2000 Å

thick.

10. The method of claim 6, further comprising removing a metal from the walls of the first trench, wherein a portion of the metal layer remains at a bottom of the first trench.

11. The method of claim 6, depositing the second silicon layer overflows the first trench.

12. The method of claim 6, further comprising chemical mechanical polishing to remove the second silicon layer where the second silicon layer overflows the first trench.

13. The method of claim 12, wherein the chemical mechanical polishing further removes portions of the metal layer outside the trench.

14. The method of claim 6, further comprising heating to react the metal layer with the first and second silicon layers to form a silicide.

15. The method of claim 6, wherein the first silicon layer and the second silicon layer comprise polysilicon.