Planarized and silicided trench contact
First Claim
1. A power MOSFET comprising:
- a substrate comprising a first trench and a second trench extending from a top surface of the substrate;
a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;
a gate structure that extends continuously in the first and second trenches, wherein a top surface of the gate structure does not extend above the top surface of the substrate, a first portion of the gate structure acts as a gate of a vertical device in the wall of the first trench, and a second portion of the gate structure forming a gate bus that includes a metal/silicide region and resides in the second trench; and
a gate contact that contacts the gate bus.
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Accused Products
Abstract
Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
42 Citations
18 Claims
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1. A power MOSFET comprising:
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a substrate comprising a first trench and a second trench extending from a top surface of the substrate;
a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;
a gate structure that extends continuously in the first and second trenches, wherein a top surface of the gate structure does not extend above the top surface of the substrate, a first portion of the gate structure acts as a gate of a vertical device in the wall of the first trench, and a second portion of the gate structure forming a gate bus that includes a metal/silicide region and resides in the second trench; and
a gate contact that contacts the gate bus. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A fabrication process for a power MOSFET comprising:
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forming a first trench in a substrate;
forming a second trench in the substrate;
doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench;
forming a conductive gate structure that extends continuously from the first trench into the second trench, wherein the gate structure comprises a first portion that is in the first trench and acts as a gate of the vertical device, and a second portion that is in the second trench and forms a gate bus that including a metal/silicide region;
planarizing a structure including the substrate and the conductive gate structure in the first and second trenches; and
depositing a contact layer after planarizing the structure, wherein the contact layer includes a first region contacting the vertical device adjacent to the first trench and a second region overlying the second trench and contacting the gate bus. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification