Packaged integrated circuits and methods of producing thereof

• US 20040183185A1
• Filed: 05/03/2004
• Published: 09/23/2004
• Est. Priority Date: 02/06/1998
• Status: Active Grant

• Current Assignee: Avner Badihi
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia, Inc.)
• Inventors: Badihi, Avner
• Granted Patent: US 7,408,249 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.

Claims

1. A packaged integrated circuit comprising:

an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;

a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane; and

a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface.

2. A packaged integrated circuit according to claim 1 and wherein said package is a chip-scale package.

3. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

4. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

5. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

6. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

7. A packaged integrated circuit assembly comprising:

a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and a plurality of electrical contacts, each connected to said electrical circuitry at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and

at least one additional electrical circuit element mounted onto and supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.

8. A packaged integrated circuit assembly according to claim 7 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of:

passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.

9. A packaged integrated circuit according to claim 7 and wherein said package is a chip-scale package.

10. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

11. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

12. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

13. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

14. A method for producing packaged integrated circuits comprising:

producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;

providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;

forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and

separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.

15. A method for producing packaged integrated circuits according to claim 14 and wherein said plurality of individual chip packages are chip scale packages.

16. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

17. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

18. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

19. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

20. A method for producing packaged integrated circuit assemblies, the method comprising:

producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;

providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;

forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;

separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages; and

mounting onto said at second planar surface of at least one of said plurality of individual chip packages, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.

21. A method of forming a packaged integrated circuit assembly according to claim 20 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of:

passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.

22. A method for producing packaged integrated circuits according to claim 20 and wherein said plurality of individual chip packages are chip scale packages.

23. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

24. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

25. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

26. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

27. A method for producing packaged integrated circuit assemblies, the method comprising:

producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;

providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;

forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;

mounting onto said at second planar surface of said wafer scale packaging, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong; and

separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.

28. A method of forming a packaged integrated circuit assembly according to claim 27 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of:

passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.

29. A method for producing packaged integrated circuits according to claim 27 and wherein said plurality of individual chip packages are chip scale packages.

30. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

31. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

32. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

33. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.