Method and integrated circuit for capacitor measurement with digital readout

• US 20040183560A1
• Filed: 03/19/2003
• Published: 09/23/2004
• Est. Priority Date: 03/19/2003
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Savage, Scott Christopher, McNitt, John Lynn, Golliher, Sean Anthony
• Granted Patent: US 6,897,673 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

On-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuits are provided. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value. The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip. A computer device reads each counter value and calculates mismatch values based on the counter values.

Claims

1. A method for on-chip measurement of capacitor values, the method comprising:

receiving, from an off-chip device, a set of digital inputs;

measuring a value for an evaluation capacitor on the chip;

providing the value at a digital output.

2. The method of claim 1, wherein the set of digital inputs includes a start signal.

3. The method of claim 2, wherein the step of measuring a value includes:

charging the evaluation capacitor;

in response to a voltage across the evaluation capacitor reaching a first threshold, starting a counter;

in response to the voltage across the evaluation capacitor reaching a second threshold, stopping the counter; and

providing the counter value to the off-chip device.

4. The method of claim 3, further comprising:

determining, by the off-chip device, an absolute capacitor value for the evaluation capacitor based on the counter value.

5. The method of claim 1, wherein the set of digital inputs includes a reset signal and a plurality of switch signals.

6. The method of claim 5, wherein the step of measuring a value includes:

(a) charging the evaluation capacitor;

(b) transferring charge from the evaluation capacitor to an integrating capacitor;

(c) incrementing a counter;

(d) repeating steps (a)-(c) until a threshold voltage is reached at the integrating capacitor; and

(e) providing the counter value to the off-chip device in response to the threshold voltage being reached at the integrating capacitor.

7. The method of claim 6, further comprising:

determining, by the off-chip device, a capacitor mismatch value for the evaluation capacitor based on the counter value.

8. The method of claim 7, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, the method further comprising:

determining, by the off-chip device, a second capacitor mismatch value for the second evaluation capacitor based on the second counter value; and

determining a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.

9. The method of claim 7, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, the method further comprising:

(a) receiving a reset signal and a set of switch signals for switching to a second evaluation capacitor;

(b) draining the integrating capacitor;

(c) resetting the counter;

(d) charging the second evaluation capacitor;

(e) transferring charge from the second evaluation capacitor to an integrating capacitor;

(f) incrementing the counter;

(g) repeating steps (d)-(f) until the threshold voltage is reached at the integrating capacitor; and

(h) providing a second counter value to the off-chip device.

10. The method of claim 9, further comprising:

determining, by the off-chip device, a second capacitor mismatch value for the second evaluation capacitor based on the second counter value; and

determining a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.

11. An apparatus for on-chip measurement of capacitor values, the apparatus comprising:

a set of digital inputs, wherein the set of digital inputs receive signals from an off-chip device;

an evaluation capacitor on the chip;

a test circuit, wherein the test circuit measures a value for the evaluation capacitor based on the set of digital inputs; and

a digital output, wherein the digital output presents the value.

12. The apparatus of claim 11, wherein the set of digital inputs includes a start signal.

13. The apparatus of claim 12, test circuit includes:

a current source, wherein current from the current source charges the evaluation capacitor;

a first comparator, wherein the first comparator determines whether a voltage across the evaluation capacitor reaches a first threshold;

a second comparator, wherein the second comparator determines whether the voltage across the evaluation capacitor reaches a second threshold; and

a counter

wherein the test circuit starts the counter in response to the voltage across the evaluation capacitor reaching the first threshold, stops the counter in response to the voltage across the evaluation capacitor reaching the second threshold, and provides the counter value to the off-chip device in response to the voltage across the evaluation capacitor reaching the second threshold.

14. The apparatus of claim 13, wherein the off-chip device determines an absolute capacitor value for the evaluation capacitor based on the counter value.

15. The apparatus of claim 11, wherein the set of digital inputs includes a reset signal and a plurality of switch signals.

16. The apparatus of claim 15, wherein the test circuit includes:

an integrating capacitor;

a first set of switches, wherein the evaluation capacitor is charged in response to the first set of switches being closed;

a second set of switches, wherein charge from the evaluation capacitor is transferred to an integrating capacitor in response to the second set of switches being closed; and

a counter,

wherein the test circuit repeatedly closes the first set of switches to charge the evaluation capacitor, closes the second set of switches to transfer charge from the evaluation capacitor to the integrating capacitor, and increments the counter until a threshold voltage is reached at the integrating capacitor and wherein the test circuit provides the counter value to the off-chip device in response to the threshold voltage being reached at the integrating capacitor.

17. The apparatus of claim 16, wherein the off-chip device determines a capacitor mismatch value for the evaluation capacitor based on the counter value.

18. The apparatus of claim 17, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, and

wherein the off-chip device determines a second capacitor mismatch value for the second evaluation capacitor based on the second counter value and determines a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.

19. The apparatus of claim 17, wherein the evaluation capacitor is a first evaluation capacitor and the capacitor mismatch value is a first capacitor mismatch value, the apparatus further comprising:

a second evaluation capacitor;

a third set of switches, wherein the second evaluation capacitor is charged in response to the third set of switches being closed; and

a fourth set of switches, wherein charge from the second evaluation capacitor is transferred to an integrating capacitor in response to the fourth set of switches being closed,

wherein the test circuit receives a reset signal and a set of switch signals for switching to a second evaluation capacitor, drains the integrating capacitor, resets the counter,

wherein the test circuit repeatedly closes the third set of switches to charge the second evaluation capacitor, closes the fourth set of switches to transfer charge from the second evaluation capacitor to the integrating capacitor, and increments the counter until a threshold voltage is reached at the integrating capacitor, and

wherein the test circuit provides the counter value to the off-chip device in response to the threshold voltage being reached at the integrating capacitor.

20. The apparatus of claim 19, wherein the off-chip device determines a second capacitor mismatch value for the second evaluation capacitor based on the second counter value, and

wherein the off-chip device determines a mismatch between the first evaluation capacitor and the second evaluation capacitor based on the first capacitor mismatch value and the second capacitor mismatch value.