Apparatus for sensing the presence of an inductive load driven by a pulse width modulated signal

• US 20040183572A1
• Filed: 03/18/2003
• Published: 09/23/2004
• Est. Priority Date: 03/18/2003
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Reasoner, Kelly J., Harmon, Duane L., Bohl, Robert H.
• Granted Patent: US 6,873,190 B2
• Time in Patent Office: Days
• US Class Current: 327/110
• CPC Class Codes: G01R 31/3278 of relays, solenoids or reed switches measuring contact resistance G01R27/205; high voltage magnetic switches G01R31/3271, G01R31/333; testing electric windings G01R31/72; monitoring of fail safe circuits H01H47/002
• CPC Class Codes: H01H 47/325 by switching regulator

Abstract

A circuit for sensing the presence of an inductive load that is particularly applicable to sensing when a solenoid is being driven by a pulse width modulation (PWM) signal. The circuit includes a high side connected transistor having an output driving a load, with the transistor driven by a PWM signal. A circulating diode is coupled to the driving output of the transistor. The circuit further comprises an operational amplifier (op amp) circuit that is coupled to the circulating diode and operates as an inverting operational amplifier (op amp). The op amp circuit charges a first capacitor when the transistor releases driving an inductive load.

Claims

1. A circuit for sensing the presence of an inductive load, comprising:

a high side connected transistor having an output driving an inductive load, said transistor driven by a pulse width modulated (PWM) signal;

a circulating diode coupled to said driving output of said transistor; and

an operational amplifier (op amp) circuit coupled to said circulating diode, said op amp circuit operating as an inverting amplifier and charging a first capacitor when said transistor is driving a load.

2. The circuit of claim 1, wherein said op amp circuit charges said first capacitor during the high of each PWM signal cycle and prevents discharge of said first capacitor during the low of each PWM signal cycle.

3. The circuit of claim 1, wherein said operation amplifier circuit comprises an amplifier that draws current through said first capacitor during the high of each cycle of said PWM signal, charging said first capacitor.

4. The circuit of claim 3, further comprising a second diode coupled to said first capacitor, said second diode being reverse-biased by said amplifier during the low of cycle of said PWM signal to block the discharge of said first capacitor.

5. The circuit of claim 1, wherein said operational amplifier circuit comprises an amplifier with ground at its positive input and a negative voltage at its negative input during the high of each said PWM signal cycle.

6. The circuit of claim 1, wherein said operation amplifier circuit comprises an amplifier and a second diode, said amplifier having ground at its positive input and a positive voltage at its negative input during the low of each cycle of said PWM signal, said second diode coupled between the output of said amplifier and having a reverse bias preventing the discharge of said first capacitor.

7. The circuit of claim 1, further comprising resistor-capacitor (RC) circuit having a second resistor and second capacitor, said circuit coupled to said capacitor as a filter.

8. The circuit of claim 7, further comprising a third resistor that permits said capacitor to discharge to ground when said transistor is not driving a load.

9. The circuit of claim 1, wherein said inductive load is a solenoid.

10. The circuit of claim 1, wherein the charge on said capacitor is measured by a processor to verify if said transistor is driving an inductive load.

11. The circuit of claim 1, wherein said amplifier circuit comprises an amplifier having a first resistor and third diode coupled to its negative input, said amplifier'"'"'s positive input coupled to ground, said first capacitor coupled across the negative input and positive output of said op amp, said circuit further comprising a second diode disposed between the output of said op amp and said first capacitor.

12. The circuit of claim 11, wherein said first resistor and said third diode are arranged to limit the positive voltage at said negative input of said amplifier.

13. A system for verifying that a signal is driving an inductive load, comprising:

a transistor driving the load, said transistor driven by a pulse width modulation (PWM) signal; and

An operational amplifier (op amp) circuit charging a first capacitor when said transistor is not driving said solenoid.

14. The system of claims 13, wherein said op amp circuit charges said first capacitor during the high of each PWM signal cycle and prevents discharge of said first capacitor during the low of each PWM signal cycle.

15. The system of claim 13, wherein said operation amplifier circuit comprises an amplifier that draws current through said first capacitor during the high of each cycle of said PWM signal, charging said first capacitor.

16. The system of claim 15, further comprising a second diode coupled to said capacitor, said diode reverse-biased by said amplifier during the low of each cycle of said PWM signal to block the discharge of said first capacitor.

17. The system of claim 15, wherein said operational amplifier circuit comprises an amplifier with ground at its positive input and a negative voltage at its negative input during the high of each said PWM signal cycle.

18. The system of claim 15, wherein said operation amplifier circuit comprises an amplifier and a second diode, said amplifier having ground at its positive input and a positive voltage at its negative input during the low of each cycle of said PWM signal, said second diode coupled between the output of said amplifier and having a reverse bias preventing the discharge of said first capacitor.

19. The system of claim 15, wherein said operational amplifier circuit comprises a first resistor and diode coupled to the negative input of said amplifier to limit the positive voltage at said negative input.

20. The system of claim 15, further comprising a resistor-capacitor network coupled to said first capacitor and having a second resistor and second capacitor coupled together as a filter.

21. The system of claim 13, wherein the load comprises a solenoid.