Voltage boosting circuit and method of generating boosting voltage, capable of alleviating effects of high voltage stress

• US 20040183586A1
• Filed: 12/09/2003
• Published: 09/23/2004
• Est. Priority Date: 12/10/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seung-Hoon, Sim, Jae-Yoon
• Granted Patent: US 7,102,423 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.

Claims

1. A voltage boosting circuit comprising:

a plurality of boosting capacitors, including a first boosting capacitor connected to a driving node and a last boosting capacitor configured to output a boosting voltage; and

a plurality of switches configured to connect the plurality of boosting capacitors in series in response to a control signal,

wherein a boosting voltage level is configured to vary as the voltage level at the driving node changes, according to a logic state of a boosting level control signal.

2. The voltage boosting circuit of claim 1, configured such that when the boosting level control signal is in a first logic state, the voltage level at the driving node changes from a ground voltage level to an external supply voltage level, thus increasing the boosting voltage level.

3. The voltage boosting circuit of claim 1, configured such that when the boosting level control signal is in a second logic state, the voltage level at the driving node is fixed at a ground voltage level, thus decreasing the boosting voltage level.

4. The voltage boosting circuit of claim 1, wherein the logic state of the boosting level control signal is configured to enter a logic high state or a logic low state in response to an external supply voltage level.

5. The voltage boosting circuit of claim 4, further comprising an external supply voltage detector configured to detect the external supply voltage level and to generate the boosting level control signal.

6. A method of generating a boosting voltage in a voltage boosting circuit that includes a plurality of boosting capacitors with a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage, and a plurality of switches that connects the plurality of boosting capacitors in series in response to a control signal, the method comprising:

increasing the boosting voltage by changing a voltage level at the driving node from a ground voltage level to an external supply voltage level when a boosting level control signal is in a first logic state; and

decreasing the boosting voltage by fixing the voltage level at the driving node to the ground voltage level when the boosting level control signal is in a second logic state.

7. The method of claim 6, further comprising:

detecting the external supply voltage level and changing the boosting level control signal to the first logic state when the external supply voltage level is less than a reference voltage level; and

detecting the external supply voltage level and changing the boosting level control signal to the second logic state when the external supply voltage level is greater than the reference voltage level.